Tags: matthieuvigne/moteus
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Automatically recover from bus-off in bootloader This is the parallel to 5d76760 but for the bootloader
Improve the semantics of non-zero target velocities When acceleration or velocity limits were enabled, the previous semantics were: "be at velocity v_f when you reach x_f" These are challenging semantics to work with, especially if the initial velocity is non-zero. For instance, if you were traveling at +20Hz at x=10, and the new target was v=20Hz, x=9.9999, the resulting trajectory would have to come to a stop, accelerate backwards, then ramp up speed in order to reach 20Hz again while passing through 9.9999. The new semantics are: "match the trajectory defined by x=x_f + t * v_f" This provides a more natural interpretation of the arguments, is more useful in practice, and requires fewer ISR cycles.
Updates to HIL tests * Lock in a 50 cycle improvement in ISR timing * Record `motor_position` along with other telemetry * When testing PWM mode, execute a short sweep to lock in position, otherwise it can get stuck in an opposite phase state * Run the ki term tests for longer, and compensate for the torque sensor lag * Increase kp/kd terms in many tests
Support prescaler==1 The delay was previously insufficient for the minimal possible prescaler.
Make ADC initialization occur at fixed phasing relative to their pres… …caler In a398d0c the initialization sequence was changed to improve performance. While that helped at the time, and I believed made the initialization robust it seems that it was possible for other phasing issues to cause problems. Notably, if ADC3 was initialized at some relative phases w.r.t. ADC1, then the ADC1 conversions would have undesired noise at some frequencies. To resolve this, we add some inline assembly that ensures that the ADC enable bit gets flipped at the exact same clock cycle relative to the prescaler every time.
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