Software Engineer, currently working on simulation of FPGA & ASIC designs. I completed a PhD in Electrical & Computer Eng. at the University of Florida in 2021
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Advanced Micro Devices (AMD)
- https://www.linkedin.com/in/joel-mandebi-77123641/
More
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CAPSL
CAPSL PublicForked from smartsystemslab-uf/CAPSL
CAPSL: The Component Authentication Process for Sandboxed Layouts Development Repo
C
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RapidWright
RapidWright PublicForked from Xilinx/RapidWright
Build Customized FPGA Implementations for Vivado
Java
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smartsystemslab-uf/smartsystemslab-uf.github.io
smartsystemslab-uf/smartsystemslab-uf.github.io PublicLab Website
CSS 3
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