read_verilog/astsimplify: copy inout ports in and out of functions/tasks #5158
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KrystalDelusion
approved these changes
Jun 4, 2025
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What are the reasons/motivation for this change?
Fixes #5157
Explain how this is achieved.
Previously,
inoutports to tasks/functions were incorrectly handled as the code assumed ports were either input or output, soinoutports would only have the values copied in, not out when they are instantiated. This change makes it two separate branches that can both be true (and uses->clonemethods so that both input and output get their own copies of the AST nodes if needed).If applicable, please suggest to reviewers how they can test the change.
I've added the testcases from the issue as well as some basic tests using each of the port types for functions/tasks. These all fail before this change.
This probably conflicts with #5135 but I don't imagine its hard to fixup either depending on which gets merged first