8000 Commits · WindhoverLabs/llvm-project · GitHub

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Commits

Commits on May 15, 2025

[RISCV] Split f64 loads/stores for RV32+Zdinx during isel instead of post-RA. (#139840)
topperc
authored
[RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in storeRegToStackSlot/loadRegFromStackSlot. NFC (#139979)
topperc
authored
[RISCV] Add test for spilling and reloading a GPRPair for Zdinx+RV32. NFC (#139983)
topperc
authored

Commits on May 13, 2025

[RISCV] Remove unneeded isel (sext_inreg $rs1, i32) isel pattern from RISCVInstrInfoXTHead.td. NFC
topperc
committed

Commits on May 12, 2025

[RISCV][Docs] Correct links to Xmipscmov and Xmipslsp specifications. NFC
topperc
committed

Commits on May 9, 2025

Commits on May 2, 2025

Commits on Apr 30, 2025

[RISCV] Remove unused tablegen multiclass. NFC
topperc
committed

Commits on Apr 29, 2025

Commits on Apr 26, 2025

[SelectionDAG] Use getExtLoadVP in PromoteIntRes_VP_LOAD. NFC
topperc
committed

Commits on Apr 25, 2025

Commits on Apr 23, 2025

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