Stars
automatic-verilog based on vimscript
Synopsys DC and Formality scripts for Opencores CAN
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for thes…
This is a project of ASIC. MSDAP is a low-cost, low-power and application specific mini stereo digital audio processor used in a hearing aid. The main function of this processor is a two-channel, 2…
This respository includes all my projects which are implemented with UVM testbenches
Implementation of Clock Gating at the RTL Level
Verilog AXI stream components for FPGA implementation
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which …
A chip that functions as an efficient 1-D median filter is implemented in this project. The ASIC design flow, from high level specification definition down to final layout extraction and simulation…
Verilog project to implement an ASIC chip from specification to tape out. Performs audio filtering, known as the Mini Stereo Digital Audio Processor (MSDAP)
SymbiFlow / autolabeler
Forked from mithro/autolabelerAdd labels to Pull Requests based on matched file patterns
A collection of great digital IC project/tutorial/website etc..
Complete UART project with specs(pdf), RTL and Testbench (Verilog)
SystemVerilog UVM testbench example
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
An ASIC designed under cell-based design flow. Developed by MATLAB for algorithm specification, by Verilog for RTL work, by Synopsys Design Compiler for logic synthesis, by Innovus for Place & Rout…
Generate a Verilog Source file and testbench file for a given Moore FSM
Python script which can generate Reg map xml, excel, verilog
通过Python开发的一套根据verilog模块生成对应TOP、test_bench、connection信号等，并在不断优化中！