Our philosophy is: think in hardware, develop hardware, take advantage of software tools.
The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.
Currently we support:
- Ghdl.
- ModelSim.
- Vhdl
- VUnit.
Soon we will support Verilog, Windows and others simulators.
- Symbolator:
pip install symbolator - TerosHDLbackend >= 0.1.0:
pip install TerosHDL - VUnit:
pip install vunit_hdl
For simulation:
- Ghdl/Modelsim
For code coverage:
- Ghdl with GCC backend.
For waveform:
- GTKWave/ModelSim
apm install terosHDL
This is an experimental feature. Not all state machines are supported.
You have a complete user manual.
Copyright (c) 2018-Present
- Carlos Alberto Ruiz Naranjo, carlosruiznaranjo@gmail.com
- Ismael Pérez Rojo, ismaelprojo@gmail.com
TerosHDL is licensed under GPLv3.