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BMS College of Engineering
- Banglore
- in/k-m-skanda-541a02291
- skanda_29
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noc_desgin Public
This project implements a 2x2 Mesh Network-on-Chip (NoC) using Verilog RTL. It consists of four routers arranged in a grid topology, enabling efficient packet-based communication between processing…
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VSDSquadron_FM Public
Forked from VSDSquadron/VSDSquadron_FMCode for VSDSquadron_FM
C MIT License UpdatedApr 3, 2025 -
vsd_sqaudron_mini_fpga Public
This repo contains four FPGA-based projects showcasing real-time UART communication, LED control, and sensor data acquisition. Designed using Verilog, Yosys, and NextPNR, running on the VSD Squadro…
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vsd_squadron_minifpga_4 Public
A Verilog project for acquiring sensor data and transmitting it via UART. Includes code, circuit diagrams, documentation, and a demo video for real-time monitoring.
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uart_loopback Public
Universal Asynchronous Receiver-Transmitter (UART) loopback on the VSD Squadcom Mini FPGA board
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This theme focuses on developing systems that interface with various sensors to collect data, process it using the FPGA, and transmit the information to external devices through communication proto…
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Neuro-Well Public
Forked from bdeekshith066/Neuro-WellYour neuro-rehabilitation platform. Recovering from a stroke, brain injury, or other neurological conditions, we offer personalized plans, virtual therapy, and support tools
Python UpdatedMar 6, 2025 -
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uart-communication- Public
A Verilog-based UART communication module implementation. This repository includes the baud rate generator, TX (transmit), and RX (receive) modules for UART. Detailed testbenches are provided to ve…
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