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This is a formally verified Moore FSM based non-overlapping sequence detector with registered outputs.
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Tools & Technologies: SystemVerilog, SystemVerilog Assertions, HW-CBMC
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Results: Assertion passing using Bounded Model Checking. Cover statements written and working visualized in the waveform.
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Files & Directories:
- seq_detector.sv: RTL design of "1011" non-overlapping sequence detector with registered outputs, Moore style. Contains formal properties and witness cover statement.
- ebmc_counter.vcd: Dump file generated by EBMC for cover statements.
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Run command:
ebmc seq_detector.sv --top seq_detector --bound 500 --reset reset==1 --vcd ebmc_counter.vcd
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Formally verified "1011" non overlapping sequence detector
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