Stars
High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.
A solver to find a solution of the 2D rectangle packing problem by simulated annealing (SA) optimization.
Circuit release of the MAGICAL project
Flora is an new GNN-based Open Source tool can apply to Dreamplace post-processing, so that can achieve faster and more accurate layout design.
Implementation of an algorithm based on the paper 'Graph Drawing by Force–Directed Placement', written by T. M. J. Fruchterman and E. M. Reingold.
ECE1387 Hardware Compiler Algorithms
[Assignment]_Analytic_Placement_and_Spreading
awesome-Analog-IC-Design-Automation
Estimates wire length of nets using different heuristic approach
Solution for 2022 ICCAD Problem D: Wirelength Driven Detailed Macro Placement
Simulated Annealing to minimize the wirelength
The Implementation for our paper: "VLSI Placement using Modified Parallel Simulated Annealing"
This repository is a clone coding of [this repository](https://github.com/The-OpenROAD-Project/RePlAce) for studying Solves electrostatic force equations using Nesterov's method.
Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
Implementation of the ePlace algorithm on the AMD Versal architecture, utilizing AIE, PL, and PS regions of the chip.
jayl940712 / GNN-DSE
Forked from UCLA-VAST/GNN-DSEDAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
Implementing Quadratic and Simulated Annealing placement for VLSI circuits design
Cell placement algorithm for VLIS - BarcelonaTech
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Placement and routing during EDA flow of VLSI designs, using Wirelength Estimation and Static Timing Analysis
Python Implementation of Heuristic Algorithms used for Placement and Routing in Chip Design
Reinforcement learning assisted analog layout design flow.
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA