Stars
A free standard cell library for SDDS-NCL circuits
A High-performance Timing Analysis Tool for VLSI Systems
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop helps to familiarise with the efabless OpenLANE VLSI design flo…
Rewrite DAG aware and-inverter graphs to share common logic wihout increasing delay
ABC: System for Sequential Logic Synthesis and Formal Verification
Course Assignment in Virtual Reality. Outdated software for 3D web graphics. If you star this repository you are most probably a time traveler from the past.