cpu/arm7: Fix undefined behavior based on invalid assembly #19619
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Contribution description
Hellooo! 🦤
In this PR a single
NOP
is added after anldm
in ARM7 common code in the scheduling management.The change is necessary because this particular
ldm
affects certain banked registers, includingR14 / lr
. The next instruction then immediately accesseslr
. This is invalid and the exact effect depends on the underlying hardware implementation. An intermediateNOP
ensures correct behaviour in such cases.The ARM docs can be found here, in section
A4.1.21 LDM (2)
. It states:Testing procedure
Without this change, on the Game Boy Advance, RIOT behaves irregularly. With the
NOP
, it works fine!If possible, this change should be tested on other ARM7 hardware as well but I do not have access to any.
Special thanks @pyropeter for spotting the extremely tiny note on this issue within the ARM docs. You saved me hours of tears! 👾