Highlights
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etiss Public
Forked from tum-ei-eda/etissExtendable Translating Instruction Set Simulator
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M2-ISA-R Public
Forked from tum-ei-eda/M2-ISA-RCoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
Python Apache License 2.0 UpdatedApr 29, 2025 -
iree Public
Forked from iree-org/ireeA retargetable MLIR-based machine learning compiler and runtime toolkit.
C++ Apache License 2.0 UpdatedApr 28, 2025 -
SCAIE-V-2.0 Public
Forked from esa-tu-darmstadt/SCAIE-V-2.0Java Apache License 2.0 UpdatedApr 12, 2025 -
llvm-project Public
Forked from llvm/llvm-projectThe LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at…
Other UpdatedApr 11, 2025 -
CoreDSL2LLVM Public
Forked from mathis-s/CoreDSL2LLVMCompiler for generating LLVM ISel Patterns from high-level instruction behavior descriptions
LLVM Other UpdatedApr 9, 2025 -
playforia-minigolf Public
Forked from WorldStarHipHopX/playforiaClient & Server for Minigolf Game known from Playforia/Playray/Appeli. Written in Java.
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cva5-sv Public
Forked from esa-tu-darmstadt/cva5-svThe CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
SystemVerilog Apache License 2.0 UpdatedMar 31, 2025 -
tvm Public
Forked from apache/tvmOpen deep learning compiler stack for cpu, gpu and specialized accelerators
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riscv-coredsl-extensions Public
Forked from DLR-SE/riscv-coredsl-extensions -
riscv-scalar-efficiency Public
Forked from riscv-admin/riscv-scalar-efficiencyAdministrative repository for the Combined Instructions SIG
Ruby Creative Commons Attribution 4.0 International UpdatedMar 11, 2025 -
OpenASIP_ISA_CoreDSL Public
Reimplementation of custom instructions from OpenASIP2.0 paper in CoreDSL2 Syntax
Apache License 2.0 UpdatedMar 11, 2025 -
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RISCV_ISA_CoreDSL Public
Forked from tum-ei-eda/RISCV_ISA_CoreDSLCoreDSL descriptions of the RISC-V ISA
1 UpdatedMar 6, 2025 -
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cv32e40p Public
Forked from openhwgroup/cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog Other UpdatedFeb 17, 2025 -
core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedFeb 17, 2025 -
xmnn-isax-flow Public
Demo scripts for XMNN Instruction Set Extension for muRISCV-NN
Shell UpdatedFeb 7, 2025 -
etiss_arch_riscv Public
Forked from tum-ei-eda/etiss_arch_riscvRISC-V architecture models for ETISS
1 UpdatedJan 16, 2025 -
riscv-tools Public
Binary distributions for RISC-V development tools (GNU/GCC Toolchain, LLVM, Simulators,...)
UpdatedDec 21, 2024 -
riscv-pk Public
Forked from riscv-software-src/riscv-pkRISC-V Proxy Kernel
C Other UpdatedNov 25, 2024 -
ml-layer-gen Public
Generate simple ML Models (Keras, Relay, TFLite) for testing effortlessly on the cmdline
Python Apache License 2.0 UpdatedNov 9, 2024 -
tflite2mermaid Public
Simple Python Script to generate Mermaid/Markdown Graphs for TFLite Models
Python Apache License 2.0 UpdatedNov 5, 2024 -
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mlonmcu-sw-mibench Public
CMake based port of https://github.com/embecosm/mibench to be used by https://github.com/tum-ei-eda/mlonmcu-sw
C Apache License 2.0 UpdatedSep 30, 2024 -
networkx Public
Forked from networkx/networkxNetwork Analysis in Python
Python Other UpdatedAug 28, 2024 -
pygraphviz Public
Forked from pygraphviz/pygraphvizPython interface to Graphviz graph drawing package
C Other UpdatedAug 27, 2024