Stars
An NTT Accelerator implementation based on ongoing research
ZPrize entry for Accelerating NTT Operations on an FPGA
Module-Lattice-based Key Encapsulation Mechanism Standard by NIST i.e. FIPS 203
Hardware implementation of Error-Correction Code in Verilog
Implemented Memory Built in self test (MBIST) in an FPGA.The design consists of a custom memory block and BIST controller which implements march-c algorithm to detect various faults.