Member of the Lab of Excellence on Microelectronics of Northeast of Brazil at UFCG. Has interests in the areas of Microelectronics, Hardware Verification.
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Universidade Federal de Campina Grande
- Campina Grande
Stars
Functional verification project for the CORE-V family of RISC-V cores.
Python packages providing a library for Verification Stimulus and Coverage
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
An example Python-based MDV testbench for apbi2c core