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Wearable measurement equipmwnt for biomachanical analysis in various athelets disciplins

C 8 1 Updated Apr 30, 2025

A 3D visualizer based on Python to analyze and validate ns-3 IEEE 802.11ad/ay implementation performance (beamforming training, throughput, SNR)

Python 11 7 Updated Jul 29, 2022

MATLAB application for ns-3 IEEE 802.11ad/ay codebook/beambook generation

10 7 Updated May 21, 2021

A quasi-deterministic (Q-D) channel implementation in MATLAB software

MATLAB 45 30 Updated Dec 19, 2022

High-fidelity implementation of the IEEE 802.11ad/ay standards in network simulator ns-3

Python 100 42 Updated Jan 20, 2022

DDS implemented on the Zynq RFSoC with sampling clock of 6.88 GHz

Tcl 1 1 Updated Oct 6, 2024

a verilog implementation of arbitrary waveform generator with Red Pitaya

Jupyter Notebook 4 1 Updated Jun 15, 2024

An arbitrary waveform generator with the Real Digital RFSoC board

Tcl 1 1 Updated Oct 28, 2024

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

Jupyter Notebook 1,077 187 Updated Sep 23, 2024

A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

Jupyter Notebook 206 35 Updated Apr 29, 2025

A Python package for 5G-NR simulations

Python 116 18 Updated Nov 1, 2024

A Python package for 5G-NR simulations

Python 2 1 Updated Sep 24, 2024

Robotics Mathematical modeling and theory with Python (learning through extensive numerical simulations and animations.)

Python 251 39 Updated AAC5 Apr 29, 2025

Drawio => VHDL and Verilog

CSS 55 10 Updated Oct 15, 2023

This repository provides a Linux kernel driver for AXI UART Lite accessed via PCIe XDMA. It enables efficient DMA-based UART communication over PCIe, ensuring low-latency and high-throughput data t…

C 12 2 Updated May 2, 2025
MATLAB 52 35 Updated Sep 18, 2024

This is test for Write the registers of RTL8211FI and receive the ethernet data

Verilog 1 1 Updated May 26, 2024

this repo contain implementation of digital AGC using matlab and vhdl

VHDL 9 2 Updated Apr 20, 2025

This repo will show how to build FFTW on Zynq

12 3 Updated Jan 31, 2025

基于ZYNQ+AD9363的开源SDR硬件

VHDL 484 136 Updated Sep 13, 2022

Open source speech codec designed for communications quality speech between 700 and 3200 bit/s. The main application is low bandwidth HF/VHF digital radio.

C 269 41 Updated Feb 22, 2025

The host program for the MMDVM

C++ 399 282 Updated May 7, 2025

Modular Open Source Radio Firmware

C 692 121 Updated Apr 27, 2025

USB cellular modem for Framework computers

2 1 Updated May 5, 2025
Python 1,599 57 Updated Apr 24, 2025

Tutorial and hardware files for the SparkFun Qwiic Pulsed Coherent Radar Sensor - Acconeer XM125. The board brings powerful 60 GHz radar technology with millimeter precision to your projects.

HTML 4 2 Updated Feb 20, 2025

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,532 600 Updated May 1, 2025
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