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This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
Coursework repository for ECE-GY 6143 Introduction to Machine Learning at NYU Tandon School of Engineering (Fall 2020).
Real-ESRGAN aims at developing Practical Algorithms for General Image/Video Restoration.
Collection of Summer 2026 tech internships!
Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology， which is to manufacture a CPU. 这是南方科技大学CS…
SUSTech 2024 Spring CS202 Course Project RISC-V 5-Stage-Pipeline CPU
SUSTech CS202 Project: A RISC-V-32 CPU that plays music. With almost all ISA instructions support. Without UART and pipeline. 118.5/100.
GTWD: Global Transcoder for WAV/FLAC/AIFF Data, project of CS205 C/C++ taught in SUSTech (2023 Fall, by Prof Feng Zheng, project selected by TA Kangrui Chen and Site Fan) (110+/100).
Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.
SUSTech CS205 CPP programming project