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ChatEDA: A Large Language Model Powered Autonomous Agent for EDA
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…
Peripheral Interface of FPGA
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
基于STM32的DCM模式下的BUCK变换器设计