BrianHGinc

BrianHG BrianHGinc

HDL Code generator.

62 followers · 8 following

BHG Ocean Fitness
Canada
18:31 (UTC -04:00)
in/brianhg-ocean-fitness

Achievements

ClintonCAT Public
Forked from WayneKeenan/ClintonCAT

Chrome Browser Extension for automatically searching Rossmann's Consumer Action Taskforce (CAT) articles for the current site being visited.

TypeScript 1 MIT License Updated Mar 21, 2025
Verilog-Floating-Point-Clock-Divider Public

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

verilog verilog-hdl verilog-components clock-generator

Verilog 20 1 Updated Feb 4, 2025
BrianHG-DDR3-Controller Public

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice

SystemVerilog 78 33 Updated Apr 8, 2024
BHG_I2C_init_RS232_debugger Public

A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.

i2c verilog rs232 verilog-hdl

SystemVerilog 6 Updated Jun 26, 2023
gpu Public
Forked from nockieboy/gpu

Collaborative project to create an advanced GPU for the Microcom computer.

SystemVerilog 4 Updated Sep 9, 2022
YM2149_PSG_system Public
Forked from nockieboy/YM2149_PSG_system

YM2149 / AY-3-8910 Programmable Sound Generator. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built in floa…

SystemVerilog 1 Updated Sep 8, 2022
adat-usb2-audio-interface Public
Forked from hansfbaier/adat-usb2-audio-interface

FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs

Python 1 Other Updated Jun 12, 2022
Minimig-AGA_SoCkit Public
Forked from somhi/Minimig-AGA_SoCkit

Minimig for SoCkit (MiSTer)

Verilog 2 Updated Jun 12, 2022
Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor Public

Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.

hex-editor verilog uart rs232 hdl

Verilog 12 1 Updated Jan 15, 2022
GPU_GEOMETRY_Testbench Public

Testbench for ' https://github.com/nockieboy/gpu ' geometry engine. Draw pixels, lines, boxes, triangles, quadrilaterals, ellipses, filled option, blitter scale and flip/mirror/rotate graphics and …

SystemVerilog 3 3 Updated Sep 13, 2021
SystemVerilog-TestBench-BPM-picture-generator Public

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of yo…

verilog systemverilog hdl test-bench systemverilog-simulation verilog-tb verilog-testbenches

SystemVerilog 5 Updated Sep 5, 2021
BrianHGinc Public

Config files for my GitHub profile.

config github-config

1 Updated Sep 5, 2021
SystemVerilog-HDMI-encoder-serializer-PLL-generator Public

SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 through Quartus Prime 20.1.

intel altera hdmi systemverilog dvi hdl quartus

SystemVerilog 9 1 Updated Sep 5, 2021
hdmi Public
Forked from hdl-util/hdmi

Send video/audio over HDMI on an FPGA

SystemVerilog 4 Other Updated Aug 22, 2021

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ClintonCAT Public

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Verilog-Floating-Point-Clock-Divider Public

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BrianHG-DDR3-Controller Public

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BHG_I2C_init_RS232_debugger Public

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gpu Public

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YM2149_PSG_system Public

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adat-usb2-audio-interface Public

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Minimig-AGA_SoCkit Public

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Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor Public

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GPU_GEOMETRY_Testbench Public

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SystemVerilog-TestBench-BPM-picture-generator Public

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BrianHGinc Public

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SystemVerilog-HDMI-encoder-serializer-PLL-generator Public

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hdmi Public

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