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This was the final project for the Microcomputer Design Course at LeTourneau University.
Implementation of CORDIC Algorithms Using Verilog
Learn digital logic design from basics to pipelines using TL-Verilog and Makerchip — fast, practical, and beginner-friendly! 🚀
Learn digital logic design from basics to pipelines using TL-Verilog and Makerchip — fast, practical, and beginner-friendly! 🚀
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Code for VSDSquadron_FM
Final Year project on design of a Nano Satellite
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
puneet / RISC-V-Assembly-Language-Programming
Forked from Apress/RISC-V-Assembly-Language-ProgrammingSource Code
Collect some IC textbooks for learning.
Implementation of adaptive filters such as BMFLC, FLC, and WFLC in C++ using Arduino
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transfer Level (RTL) to the Graphical Data System (GDS)
Resources for the master thesis done in the autumn of 2019. Title of thesis: IMPLEMENTATION OF A NEURAL NETWORK ON A MICROCONTROLLER FOR CONSTRUCTION OF SMART NOISE REDUCING HEADPHONES
A simple neural network prototype with a single hidden layer for Arduino microcontroller.
In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V Single Cycle.
hardware design of universal NPU(CNN accelerator) for various convolution neural network