8000 AkshayXPatil (AkshayXPatil) / Repositories · GitHub

Address: [go: up one dir, main page]

Include Form Remove Scripts Accept Cookies Show Images Show Referer Rotate13 Base64 Strip Meta Strip Title Session Cookies

More Web Proxy on the site http://driver.im/

Skip to content

Navigation Menu

Appearance settings

Explore
By company size
By use case
By industry
View all solutions
Topics
- AI
- DevOps
- Security
- Software Development
- View all
Explore
- GitHub Sponsors
  Fund open source developers
- The ReadME Project
  GitHub community articles
Repositories
- Enterprise platform
  AI-powered developer platform
Available add-ons
Pricing

Search code, repositories, users, issues, pull requests...

Search

Clear

Search syntax tips

Provide feedback

We read every piece of feedback, and take your input very seriously.

Include my email address so I can be contacted

Saved searches

Use saved searches to filter your results more quickly

Name

Query

To see all available qualifiers, see our documentation.

Appearance settings

You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session. You switched accounts on another tab or window. Reload to refresh your session.

Dismiss alert

AkshayXPatil Follow

Overview Repositories 5 Projects 0 Packages 0 Stars 0

More

Overview
Repositories
Projects
Packages
Stars

AkshayXPatil

Follow

🎯

Focusing

Akshay Nandkumar Patil AkshayXPatil

🎯

Focusing

Follow

I am an MSEE student from The University of Texas at Dallas. I am here to share some projects that I have completed throughout the course.

16 followers · 10 following

Dallas, TX
https://www.linkedin.com/in/akshayxpatil/

Block or report AkshayXPatil

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Add an optional note:

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Overview Repositories 5 Projects 0 Packages 0 Stars 0

More

Overview
Repositories
Projects
Packages
Stars

Type All

Select type

All Sources Forks Archived Can be sponsored Mirrors Templates

Language All

Select language

All Verilog SystemVerilog C++

Sort Last updated

Select order

Last updated Name Stars

Physical-Layout-Design Public

Complete design of USART interface with baud rate selection

scripting rtl verilog uart vlsi-physical-design gds2 pnr

Verilog 4 2 Updated Aug 24, 2022
MSDAP Public

Complete design of a Mini Stereo Digital Audio Processor

asic perl scripting tcl rtl convolution fir-filter

Verilog 3 4 Updated Jan 3, 2019
Design-verification Public

UVM and Systemverilog based test benches for functional verification of a RAM module

verification systemverilog hdl uvm

SystemVerilog 6 5 Updated Jan 2, 2019
Standard-cell-placement-engine Public

Simulated Annealing based fixed-die standard cell placement engine for IBM benchmark netlists

cplusplus cad vlsi design-automation simmulated-annealing

C++ 5 5 Updated Jan 2, 2019
FM-partioner Public

Fiduccia-Mattheyses method to bi-partition the ISPD 2016 benchmarks and minimized the cutset

cplusplus vlsi fiduccia-mattheyses design-automation

C++ 5 4 Updated Jan 2, 2019

Footer

© 2025 GitHub, Inc.

Footer navigation

Terms
Privacy
Security
Status
Docs
Contact

You can’t perform that action at this time.

0