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Raptor Public
Forked from os-fpga/RaptorRaptor end-to-end FPGA Compiler and GUI
Verilog Other UpdatedDec 3, 2024 -
yosys_verific_rs Public
Forked from os-fpga/yosys_verific_rsYosys + (Optional) Verific Integration
Verilog Other UpdatedDec 3, 2024 -
yosys-rs-plugin Public
Forked from os-fpga/yosys-rs-pluginRapidsilicon's Yosys Plugin
Verilog Other UpdatedNov 28, 2024 -
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RISCV_5_Stage_Pipelined_CPU Public
This is RISCV 5-stage pipelined CPU core implementation in System Verilog. It has Fetch, Decode, Execute, Memory and write back pipelined stages. It also contains a hazard unit which handles the da…
SystemVerilog UpdatedOct 14, 2024 -
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Single_Cycle_RISCV_CPU Public
This is single cycle RSICV CPU which implements 30 instructions in RV32I
SystemVerilog UpdatedOct 6, 2024 -
FPGA_PRIMITIVES_MODELS Public
Forked from os-fpga/FPGA_PRIMITIVES_MODELSVerilog Other UpdatedOct 6, 2024 -
This repository contains verification projects using UVM based environment. I have implemented these projects during my UVM base verification learning journey.
SystemVerilog UpdatedJun 29, 2024 -
RTL_Benchmark Public
Forked from os-fpga/RTL_BenchmarkThis repository contains the benchmarks.
Verilog Other UpdatedMay 30, 2024 -
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A RISCV CPU Core is built consists 31 base instructions using-TL-Verilog
UpdatedFeb 19, 2024 -
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wb_slave_core2 Public
Forked from hassaankhalid1996/wb_slave_core2Designing a layered test-bench for the wishbone slave interface.
SystemVerilog UpdatedJun 28, 2020
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