MatchLib is a SystemC/C++ library of commonly-used hardware functions and components that can be synthesized by most commercially-available HLS tools into RTL.
Doxygen-generated documentation can be found here.
MatchLib is based on the Connections latency-insensitive channel implementation. Connections is included with the Catapult HLS tool and is available open-source on HLSLibs. Additional documentation on the Connections latency-insensitive channel implementation can be found in the Connections Guide.
MatchLib is regressed against the following tool/dependency versions:
gcc- 10.3.0boost- 1.68.0doxygen- 1.8.11make- 3.82binutils- 2.34catapult- 2024.1_1systemc- 2.3.3 (included with Catapult)connections- 2.1.1 (included with Catapult)vcs- 2023.03verdi- 2023.03python- 3.6.1rapidjson- 06d58b9 (included as submodule)
Makefiles assume the appropriate definition of the following environment variables:
BOOST_HOMECATAPULT_HOMEVCS_HOMENOVAS_INST_DIR
In addition, the boost and systemc library locations are expected to be in LD_LIBRARY_PATH.
cd cmod/<module>
make
make run
cd cmod
make -f regress_Makefile
cd hls/<module>
make
cd hls
make -f regress_Makefile
cd hls/<module>
make cdc
cd hls
make -f regress_Makefile RUN_CDESIGN_CHECKER=1
cmod/include/*.hcontains header files for functions and classes from MatchLibcmod/<module>sub-directories contain SystemC modules from MatchLibcmod/examples/<module>sub-directories contain SystemC example modulescmod/unittests/<module>sub-directories contain SystemC wrappers, testbenches and tests for various MatchLib functions, classes, and moduleshls/<module>sub-directories contain HLS scripts for modulesdoccontains Makefiles for building Doxygen-based documentation
HLS_CATAPULT- Select if Catapult is selected as the HLS target. Catapult header files will not be included if not set. If enabled,NVINTis defined asac_int. If disabled,NVINTis defined assc_int. Currently MatchLib only supports Catapult, soHLS_CATAPULTmust be set.HLS_ALGORITHMICC- Set to enable AlgorithmicC-specific optimizations in the code.HLS_STRATUS- Set to indicate that HLS is being performed with Stratus tool. This disables Catapult-specific flags and optimizations like the use of ac_types. This feature is not fully tested.SC_INCLUDE_DYNAMIC_PROCESSES- Set to enable SystemC dynamic processes.__SYNTHESIS__- Set by Catapult during the HLS flow (but not during sc_verify)._SYNTHESIS_- Flag to set when calling the HLS tool during both HLS and sc_verify.SKIP_LV2TYPE- Set to enable complex types to be stored as logic vectors in certain design-specific cases.COV_ENABLE- Set to enable coverage collection with CTC.NVHLS_VERIFY_ISVCSMX- Set for standalone VCS-MX co-simulations of SystemC with Catapult-generated RTL. Do not use in SystemC simulation or Catapult sc_verify.ENABLE_SYNC_RESET- Enables synchronous, active-low reset instead of asynchronous, active-low reset in MatchLib.NVHLS_CONTINUE_ON_ASSERT- Raise anSC_ERRORon assertion failures rather than exiting. Do not use during Catapult HLS, only during simulation.
Additional macros such as AUTO_PORT, FORCE_AUTO_PORT, CONNECTIONS_ACCURATE_SIM, CONNECTIONS_FAST_SIM, CONNECTIONS_SIM_ONLY, CONN_RAND_STALL, CONN_RAND_STALL_PRINT_DEBUG, CONNECTIONS_ASSERT_ON_QUERY, and DISABLE_PACER may be used in MatchLib. These macros are primarily defined, implemented, and documented in Connections. For more detail on these macros, see the Connections documentation.
Many of the flags above are design-specific, and so are typically codified into design Makefiles. However, some of the variables pertain to different simulation modes, and it is desirable to simulate the same design under different settings for different purposes. Accordingly, we provide the following command-line environment flags for use with the cmod or hls steps:
SIM_MODE- Set this variable to 1 (default) to use Connections sim-accurate mode, so that Connections ports and channels simulated in SystemC closely match the cycle-by-cycle behavior of their HLS-generated RTL counterparts. Set this variable to 2 to enable a TLM-based Connections mode that is faster to simulate but does not track the cycle behavior of HLS-generated RTL as closely. Set this variable to 0 to directly simulate the synthesized representation of Connections ports and channels (not recommended, as it may result in spurious failures).RAND_STALL- Set this variable to 1 to enable random stalling on Connections ports and channels. Set to 0 (default) to disable random stalling.DEBUG_LEVEL- Set to control the amount of debug information printed to the command line during execution. In general, higher debug levels will enable debug information from additional modules.NVHLS_RAND_SEED- Set to a number to use as a fixed seed for nvhls_rand (defaults to 0).
To accurately simulate expected RTL performance, use the default settings. For robust verification, simulate with four different modes: both SIM_MODE=1 and SIM_MODE=2, with random stalling both enabled and disabled and various random seeds.
We welcome feedback and contributions from the open-source hardware community. If you have a question or problem, please file an issue on GitHub. To contribute bugfixes or new features, submit a pull request. For business inquiries, please contact researchinquiries@nvidia.com. For press and other inquiries, please contact Hector Marinez at hmarinez@nvidia.com.
MatchLib originated as a project of NVIDIA Research.
Contributors to the initial open-source release (alphabetical): Jason Clemons, Christopher Fletcher, Davide Giri, Ben Keller, Brucek Khailany, Alicia Klinefelter, Evgeni Krimer, Hyoukjun Kwon, Ziyun Li, Michael Pellauer, Nathaniel Pinckney, Antonio Puglielli, Sophia Shao, Shreesha Srinath, Gopalakrishnan Srinivasan, Christopher Torng, Rangharajan Venkatesan, Sam Xi
Portions of MatchLib are derived from code in Mentor Graphics' Algorithmic C Datatypes v3.7.1 (also released under the Apache 2.0 license). See individual file headers for details.
MatchLib's back annotation feature is dependent on RapidJSON released under the MIT License.
If used for research, please cite the DAC paper:
Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, and Brian Zimmer, "A modular digital VLSI flow for high-productivity SoC design," in Proceedings of the ACM/IEEE Design Automation Conference, June 2018.