8000 MaxWei250 (Zhang Jiawei) / Starred · GitHub
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  • ShanDong University
  • No. 1500, Shunhua Road, Jinan Hi-Tech Zone, Shandong University Software Park Campus
  • 22:00 (UTC +08:00)

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Conquer Any Code in VSCode: One-Click Comments, Conversions, UI-to-Code, and AI Batch Processing of Files! 在 VSCode 中征服任何代码:一键注释、转换、UI 图生成代码、AI 批量处理文件!💪

TypeScript 2,613 189 Updated May 6, 2025

在vscode上的数字设计开发插件

Verilog 377 23 Updated Jan 27, 2023

H265 decoder write in verilog, verified on Xilinx ZYNQ7035

SystemVerilog 71 39 Updated Sep 2, 2021

xk265:HEVC/H.265 Video Encoder IP Core (RTL)

Verilog 249 80 Updated Apr 9, 2023

A lightweight image converter which supports PNG, PNM, BMP, QOI, JPEG-LS, and H.265 intra-frame.

C 50 6 Updated Jun 7, 2025

HElib is an open-source software library that implements homomorphic encryption. It supports the BGV scheme with bootstrapping and the Approximate Number CKKS scheme. HElib also includes optimizati…

C++ 3,198 762 Updated Aug 1, 2024

Microsoft SEAL is an easy-to-use and powerful homomorphic encryption library.

C++ 3,793 733 Updated Apr 2, 2025

This is the development repository for the OpenFHE library. The current stable version is 1.2.4 (released on March 21, 2025). The current development version is 1.3.0 (released on May 21, 2025).

C++ 917 232 Updated Jun 6, 2025

CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.

Verilog 31 4 Updated Feb 21, 2024

Homomorphic Encryption Accelerator Project for the Stanford EE372 tapeout class. We implement the BGV encryption scheme with Skywater-PDK (130nm).

Verilog 8 1 Updated Jul 14, 2023
41 11 Updated Jul 22, 2022
Verilog 9 2 Updated Feb 22, 2024

risc-v isa extension and rlwe acceleration

SystemVerilog 1 Updated Mar 8, 2018

Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms

Verilog 27 6 Updated Dec 10, 2021

FPGA implementation of Chinese SM4 encryption algorithm.

Verilog 53 26 Updated Mar 11, 2018

Play time!

Jupyter Notebook 199 70 Updated Sep 13, 2024

Undergraduate digital circuit laboratory

SystemVerilog 27 2 Updated Jan 4, 2024

All in one vscode plugin for HDL development

VHDL 795 62 Updated May 26, 2025

计算机保研交流群(QQ群号:605176069)

HTML 1,445 163 Updated Dec 30, 2022

Video Stream Scaler

Verilog 40 14 Updated Jul 17, 2014

AXI协议规范中文翻译版

151 33 Updated Jul 5, 2022

FPGA project

VHDL 222 48 Updated Apr 5, 2022

This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code a…

C 32 10 Updated Mar 1, 2023

implementation of opencv sgbm(disparity map extract) on FPGA

SystemVerilog 11 2 Updated Oct 27, 2021

Free monospaced font with programming ligatures

Clojure 79,168 3,142 Updated May 16, 2025

33F5 Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

Verilog 706 125 Updated Nov 13, 2024
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