A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC
This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset ...
A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system
In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, ...
Compact and low power ADCs for a MEMS-based probe storage device
In this paper, we investigate the most appropriate ADC for an array of probe storage devices. Power consumption and area are crucial in this application, since one ADC is associated with each read channel. The read-channel specifications of the probe ...
Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active---passive loop-filters
The design and optimization methodology for CT ΣΔ modulators with hybrid Active---Passive (AP) loop-filters is indicated in this work. From the discussion, by appropriately scaling the passive filter gain and cooperating with a single-bit quantizer, the ...
A full-band UWB common-gate band-pass noise matched gm-boosted series peaked CMOS differential LNA
This paper presents a low-power noise-matched fully-differential common-gate (CG) low noise amplifier (LNA) for ultrawideband receiver operating in the full 3.1---10.6 GHz band. Performance was optimized by employing the transconductance ` g m ' ...
A feed-forward AGC circuit with 48 dB-gain range, 1.2 μs minimum settling time for WiMAX receiver
The IEEE 802.16 standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in WiMAX environment. The stringent settling-time constraints of OFDM signals make conventional closed-loop feedback AGC impractical for WiMAX ...
A broadband linear-in-decibel variable gain amplifier with low gain error
A new circuit architecture for broadband digitally controlled variable gain amplifier (VGA) is introduced in this paper. The gain of the VGA is controlled precisely by using a resistor ladder attenuator and a closed-loop fine gain control block ...
A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology
A fast-settling all-digital phase-locked loop (ADPLL) is presented in this paper. We propose two techniques for reducing the settling time of an ADPLL, i.e. the oscillator tuning word (OTW) presetting technique and counter-based mode switching ...
A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOS
This paper presents a low phase noise integer-N phase-locked loop (PLL) for V-band signal generation. To enhance the frequency stability, we use a new class of Vackar voltage-controlled oscillator (VCO) in the PLL. The Vackar VCO achieves a low phase ...
A low-power voltage-controlled oscillator with current-switched technique
A low-power voltage-controlled oscillator (VCO) with current-switched technique is presented. The circuit is implemented in 0.18-μm CMOS technology. In the design, a large inductor is used for low-power and low-phase-noise application, whereas a ...
Wide-locking range ÷3 series-tuned injection-locked frequency divider
A new wide locking range series-tuned (ST) divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The 3 ILFD circuit is realized with a ST cross-coupled n-core MOS LC -tank oscillator. Two direct-...
A power-efficient 2-dimensional on-chip eye-opening monitor for Gbps serial links
This paper investigates the drawbacks of widely used rectangular eye-opening monitors (EOMs) and proposes a new power-efficient half hexagon EOM for Gbps serial links. The proposed EOM outperforms rectangular EOMs by providing a better control of data ...
An 8-bit 208 MS/s SAR ADC in 65 nm CMOS
An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a ...
An 8-bit 1 GS/s folding and interpolating ADC with a base-4 architecture
A base-4 architecture for folding and interpolating ADC is proposed. It employs cascaded folding and interpolating topology with both the folding factors and interpolating factors of 4. Duo to that the base-4 folding and interpolating has an intrinsic ...
Harmonic and intermodulation performance of MoS2FET- and GFET-based amplifiers
This paper presents a simple mathematical model for the output---input voltage characteristic of the graphene field effect transistor (GFET)- and the molybdenum disulfide field effect transistor (MoS2FET)-based inverting amplifiers. The model, basically ...
Gate-leakage compensation scheme for programmable SI-DAC of ΣΔ modulator in deep sub-micron
A gate-leakage compensation scheme is proposed to solve the gate-leakage current issue caused by large-size current-source transistors in multi-bit switched-current (SI) DACs of the continuous-time ΣΔ modulator in deep sub-micron process without extra ...