Tensor Computation: A New Framework for High-Dimensional Problems in EDA
Many critical electronic design automation (EDA) problems suffer from the curse of dimensionality, i.e., the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by ...
The STREAM Mechanism for CPS Security The Case of the Smart Grid
Cyber-physical systems (CPSs) integrate computation, communication, and physical capabilities to interact with the physical world and humans. In this paper, we develop a novel strategic resource availability management (STREAM) system to improve ...
Delay-Bounded Intravehicle Network Routing Algorithm for Minimization of Wiring Weight and Wireless Transmit Power
As the complexity of vehicular distributed systems increases rapidly, several hundreds of devices are being placed in a modern automotive system. With the increase in wiring cables connecting these devices, the weight of a vehicle increases ...
Toward Robust Vehicle Platooning With Bounded Spacing Error
Intelligent transportation has become an essential field of cyber-physical systems. Among various intelligent transportation technologies, the automated highway system (AHS) has its unique advantage of being able to coordinate a platoon of vehicles as a ...
Memory-Aware Embedded Control Systems Design
Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the ...
Dynamic Allocation Mechanism to Reduce Read Latency in Collaboration With a Device Queue in Multichannel Solid-State Devices
In this paper, we focus on read operations in flash memory, which have received less attention than write operations. To reduce read latency, we propose a read-aware dynamic allocation mechanism for multichannel solid-state devices. The proposed ...
Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids
Electromigration (EM) is a growing concern in on-chip interconnects, particularly in the computing and automotive domains. EM can cause wire resistances in a circuit to increase, which may result in circuit performance failure within the lifetime of a ...
Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling
This paper proposes a graph-based algorithm for solving the adjustable delay buffer (ADB) allocation problem optimally under useful clock skew scheduling. Our algorithm supports additional features: extending the optimality to the allocation of ADBs ...
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis
Security against hardware Trojan that is capable to change the computational output value is accomplished by employing dual modular redundant (DMR) schedule during high level synthesis (HLS). However, building a DMR for Trojan security is nontrivial and ...
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns
This paper presents Star-EDT—a novel deterministic test compression scheme. The proposed solution seamlessly integrates with EDT-based compression and takes advantage of two key observations: 1) there exist clusters of test vectors that can detect many ...
Rapid Analysis of Active Cell Balancing Circuits
Active cell balancing improves the performance of a battery pack by transferring charge from one cell to another. Associated design questions require multiple simulations with 100 cells over several hours. Since the most efficient transfer methods ...
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
This paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as ...