Accelerating Markovian analysis of asynchronous systems using state compression
This paper presents a methodology to speed up the stationary analysis of large Markov chains that model asynchronous systems. Instead of directly working on the original Markov chain, we propose to analyze a smaller Markov chain obtained via a novel ...
A methodology for concurrent process-circuit optimization
In order to optimize integrated circuit designs, it is critical not only for circuit designers to adjust circuit geometries but also for process developers to adjust device characteristics for optimal overall system performance. This paper describes ...
Equivalence checking of combinational circuits using Boolean expression diagrams
The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of computer-aided design (CAD) applications, for example when checking the ...
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
We describe the use of symmetry for verification of transistor-level circuits by symbolic trajectory evaluation (STE). We present a new formulation of STE which allows a succinct description of symmetry properties in circuits, Symmetries in circuits are ...
VHDL semantics and validating transformations
Formal models are used to provide an unambiguous definition of the semantics of very high speed integrated circuit hardware description language (VHDL) and to prove equivalences of VHDL programs. This paper presents a formal model of the dynamic ...
Modeling and formal verification of the Fairisle ATM switch fabric using MDGs
In this paper, we present several techniques for modeling and formal verification of the Fairisle asynchronous transfer mode (ATM) switch fabric using multiway decision graphs (MDGs). MDGs represent a new class of decision graphs which subsumes Bryant's ...
Sequence compaction for power estimation: theory and practice
Power estimation has become a critical step in the design of today's integrated circuits (ICs). Power dissipation is strongly input pattern dependent and, hence, to obtain accurate power values one has to simulate the circuit with a large number of ...
Optimal shape function for a bidirectional wire under Elmore delay model
In this paper, we determine the optimal shape function for a bidirectional wire under the Elmore delay model. Given a bidirectional wire of length L, let f(x) be the width of the wire at position x, 0⩽x⩽L. Let TDR be the right-to-left delay. Let ...
Equivalent circuit model of resistive IC sensors derived with the box integration method
We present an automatic method to produce compact equivalent circuit models of spatially inhomogeneous resistors. Local variations in space of the resistivity due to physical interactions such as magnetic fields or mechanical stress are automatically ...
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm which can minimize total area subject to maximum delay bound. The ...
Test set selection for structural faults in analog IC's
In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an ...
Static test compaction for synchronous sequential circuits based on vector restoration
We propose a new static test compaction procedure for synchronous sequential circuits. The procedure belongs to the class of procedures that omit test vectors from a given test sequence in order to reduce its length without reducing the fault coverage. ...
A fast nonenumerative automatic test pattern generator for path delay faults
This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern ...