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Author’s Latest Publications
- article
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
- K. Sakuma,
- P. S. Andry,
- C. K. Tsang,
- S. L. Wright,
- B. Dang,
- C. S. Patel,
- B. C. Webb,
- J. Maria,
- E. J. Sprogis,
- S. K. Kang,
- R. J. Polastre,
- R. R. Horton,
- J. U. Knickerbocker
November 2008IBM Journal of Research and Development, Volume 52, Issue 6https://doi.org/10.1147/JRD.2008.5388567 - article
Three-dimensional silicon integration
- J. U. Knickerbocker,
- P. S. Andry,
- B. Dang,
- R. R. Horton,
- M. J. Interrante,
- C. S. Patel,
- R. J. Polastre,
- K. Sakuma,
- R. Sirdeshmukh,
- E. J. Sprogis,
- S. M. Sri-Jayantha,
- A. M. Stephens,
- A. W. Topol,
- C. K. Tsang,
- B. C. Webb,
- S. L. Wright
November 2008IBM Journal of Research and Development, Volume 52, Issue 6https://doi.org/10.1147/JRD.2008.5388564 - article
3D chip stacking with C4 technology
- B. Dang,
- S. L. Wright,
- P. S. Andry,
- E. J. Sprogis,
- C. K. Tsang,
- M. J. Interrante,
- B. C. Webb,
- R. J. Polastre,
- R. R. Horton,
- C. S. Patel,
- A. Sharma,
- J. Zheng,
- K. Sakuma,
- J. U. Knickerbocker
November 2008IBM Journal of Research and Development, Volume 52, Issue 6https://doi.org/10.1147/JRD.2008.5388560 - article
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
November 2008IBM Journal of Research and Development, Volume 52, Issue 6https://doi.org/10.1147/JRD.2008.5388558 - article
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
- J. U. Knickerbocker,
- P. S. Andry,
- L. P. Buchwalter,
- A. Deutsch,
- R. R. Horton,
- K. A. Jenkins,
- Y. H. Kwark,
- G. McVicker,
- C. S. Patel,
- R. J. Polastre,
- C. Schuster,
- A. Sharma,
- S. M. Sri-Jayantha,
- C. W. Surovic,
- C. K. Tsang,
- B. C. Webb,
- S. L. Wright,
- S. R. McKnight,
- E. J. Sprogis,
- B. Dang
July 2005IBM Journal of Research and Development, Volume 49, Issue 4/5