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- Article
C-TAR: A Compositional Threat Analysis and Risk Assessment Method for Infrastructure-Based Autonomous Driving
Computer Security. ESORICS 2023 International Workshops•September 2023, pp 159-175• https://doi.org/10.1007/978-3-031-54129-2_10AbstractAutonomous Vehicles rely heavily on their sensors’ information to navigate correctly. Autonomous driving requires the support of infrastructure-based systems to provide extra sensor information, which cannot be collected by vehicles. We expect ...
- Article
Towards a Digital Twin Architecture with Formal Analysis Capabilities for Learning-Enabled Autonomous Systems
- Anastasios Temperekidis,
- Nikolaos Kekatos,
- Panagiotis Katsaros,
- Weicheng He,
- Saddek Bensalem,
- Hisham AbdElSabour,
- Mohamed AbdElSalam,
- Ashraf Salem
Modelling and Simulation for Autonomous Systems•October 2022, pp 163-181• https://doi.org/10.1007/978-3-031-31268-7_10AbstractDigital twins are increasingly used to test and verify complex cyber-physical systems. The main reason is their flexibility in combining multiple behavior domains to faithfully model all effects of the computing elements, their physical ...
- research-article
Emulation and verification framework for MPSoC based on NoC and RISC-V
Design Automation for Embedded Systems, Volume 26, Issue 3-4•Dec 2022, pp 133-159 • https://doi.org/10.1007/s10617-022-09265-1AbstractNowadays, embedded systems have multiprocessing capabilities to meet the complexity of modern applications, such as signal processing and multimedia. However, as the embedded system’s functionality expands, complexity increases and numerous ...
- research-article
On Error Injection for NoC Platforms: A UVM-based Practical Case Study
- Sameh El-Ashry,
- Hala Ibrahim,
- Moamen A. Ibrahem,
- Mostafa Khamis,
- Ahmed Shalaby,
- Mohamed AbdElsalam,
- M. Watheq El-Kharashi
NoCArc '17: Proceedings of the 10th International Workshop on Network on Chip Architectures•October 2017, Article No.: 2, pp 1-6• https://doi.org/10.1145/3139540.3139544Error injection has become critically important for testing the reliability of the hardware of any system. Measuring how a design under test reacts to different error injection methodologies is very essential for verification engineers to design ...
- research-article
On kernel acceleration of electromagnetic solvers via hardware emulation
- M. Tarek Ibn Ziad,
- Mohamed Hossam,
- Mohamad A. Masoud,
- Mohamed Nagy,
- Hesham A. Adel,
- Yousra Alkabani,
- M. Watheq El-Kharashi,
- Khaled Salah,
- Mohamed AbdelSalam
Computers and Electrical Engineering, Volume 47, Issue C•October 2015, pp 96-113 • https://doi.org/10.1016/j.compeleceng.2015.08.017We present an emulation-based accelerator for EM simulations in metamaterials.We propose two hardware designs to solve systems of linear equations from the FEM.Both presented designs are run on a physical Veloce 1 emulator from Mentor Graphics.Timing ...
- Article
A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML
MTV '14: Proceedings of the 2014 15th International Microprocessor Test and Verification Workshop•December 2014, pp 61-66• https://doi.org/10.1109/MTV.2014.15System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the ambiguity of design specifications specified by different ...
- Article
A novel approach for system level synthesis of multi-core system architectures from TPG models
AICCSA '11: Proceedings of the 2011 9th IEEE/ACS International Conference on Computer Systems and Applications•December 2011, pp 268-275• https://doi.org/10.1109/AICCSA.2011.6126600A multi-processor system is an integrated circuit containing multiple processor cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on a single chip. In this paper, we present a novel ...
- Article
TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip
MTV '11: Proceedings of the 2011 12th International Workshop on Microprocessor Test and Verification•December 2011, pp 1-4• https://doi.org/10.1109/MTV.2011.9Easy, efficient, and automated technique for rapid architectural exploration is achieved using Transaction Level Modeling (TLM) methodology. Architecture evaluation is performed in early stage of the design. An approach for TLM architecture exploration ...