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Most BIST architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative approaches either ...

A design method for random single input change sequence based on ALFSR with primitive multinomial was proposed in this paper. ALFSR can not only generate sequence at any initial state and can be design easily without extra signals but generate RSIC ...

Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo -randomly. We ...

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by ...

In this paper we show, that the statistical qualities of cryptographic basic operations are the reason for the excellent pseudo-random testability of cryptographic processor cores. For the examination typical basic operations of modern cryptographic ...

While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo-random testing of bridging faults and describes a means for achieving high fault coverage in a built-in self-test (BIST) environment. Bridging ...

This paper proposes a new technique, called scan-mapping, for applying two-pattern tests in a standard scan design environment. Scan-mapping is performed by shifting the first pattern (V/sub 1/) into the scan path and then using combinational mapping ...