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- keynoteApril 2024
Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA.
FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPage 1https://doi.org/10.1145/3626202.3644812FPGAs are not just computational workhorses -- they are virtual laboratories for innovation -- a glimpse into our spatial and temporal computing future. No other technology allows you to break computations down into their underlying logical atoms so ...
- short-paperApril 2024
Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis
FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPages 176–182https://doi.org/10.1145/3626202.3637578Whilst Field-Programmable Gate Arrays (FPGAs) have been popular in accelerating high-frequency financial workload for many years, their application in quantitative finance, the utilisation of mathematical models to analyse financial markets and ...
- research-articleApril 2024
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPages 211–222https://doi.org/10.1145/3626202.3637561Field-programmable gate arrays (FPGAs) provide opportunities for adopting cutting-edge microarchitectural technologies to accelerate emerging applications. However, it remains challenging to program FPGAs. On one hand, hardware description languages (...
- short-paperDecember 2023
Demo: Enabling DNN Inference in the Network Data Plane
- Siddhartha,
- Justin Tan,
- Rajesh Bansal,
- Huang Chee Cheun,
- Yuta Tokusashi,
- Chong Yew Kwan,
- Haris Javaid,
- Mario Baldi
EuroP4 '23: Proceedings of the 6th on European P4 WorkshopPages 65–68https://doi.org/10.1145/3630047.3630191Advancements in programmable packet processing technologies have fostered innovation across a range of networking applications. Integration of deep neural networks (DNN) in the network data plane, however, has remained largely unaddressed due to the high ...
- panelFebruary 2023
Open-source and FPGAs: Hardware, Software, Both or None?
FPGA '23: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPage 149https://doi.org/10.1145/3543622.3579026Following the footsteps of the open-source software movement that is at the foundation of many fundamental infrastructures today, e.g., Linux, the internet, etc., a growing amount of open-source hardware initiatives have been impacting our field, e.g., ...
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- research-articleFebruary 2022
How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics
FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 13–23https://doi.org/10.1145/3490422.3502371Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed),...
- research-articleFebruary 2021
A Framework for Customizable FPGA-based Image Registration Accelerators
FPGA '21: The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 251–261https://doi.org/10.1145/3431920.3439291Image Registration is a highly compute-intensive optimization procedure that determines the geometric transformation to align a floating image to a reference one. Generally, the registration targets are images taken from different time instances, ...
- research-articleMarch 2020
HEAX: An Architecture for Computing on Encrypted Data
ASPLOS '20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 1295–1309https://doi.org/10.1145/3373376.3378523With the rapid increase in cloud computing, concerns surrounding data privacy, security, and confidentiality also have been increased significantly. Not only cloud providers are susceptible to internal and external hacks, but also in some scenarios, ...
- research-articleMarch 2020
Fleet: A Framework for Massively Parallel Streaming on FPGAs
ASPLOS '20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 639–651https://doi.org/10.1145/3373376.3378495We present Fleet, a framework that offers a massively parallel streaming model for FPGAs and is effective in a number of domains well-suited for FPGA acceleration, including parsing, compression, and machine learning. Fleet requires the user to specify ...
FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators
ASPLOS '20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating SystemsPages 219–234https://doi.org/10.1145/3373376.3378459Pattern matching, especially for complex patterns with many variations, is an important task in many big-data applications and maps well to finite automata. Recently, a variety of research has focused on hardware acceleration of automata processing, ...
- panelFebruary 2020
What To Do With Datacenter FPGAs Besides Deep Learning
FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 26https://doi.org/10.1145/3373087.3375885FPGAs have been deployed in datacenters worldwide and are now available for use by in both public and private clouds. Enormous focus has been given to optimizing machine learning workloads for FPGAs, especially for deep neural networks (DNNs) in areas ...
- short-paperFebruary 2020
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 51–57https://doi.org/10.1145/3373087.3375320The domain-specific language (DSL) for image processing, Halide, has generated a lot of interest because of its capability of decoupling algorithms from schedules that allow programmers to search for optimized mappings targeting CPU and GPU. ...
- short-paperFebruary 2020
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs
FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 204–210https://doi.org/10.1145/3373087.3375318Embedded and cyber-physical systems are pervading all aspects of our lives, including sensitive and critical ones. As a result, they are an alluring target for cyber attacks. These systems, whose implementation is often based on reconfigurable hardware, ...
- research-articleMay 2019
Thermal Fingerprinting of FPGA Designs through High-Level Synthesis
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSIPages 331–334https://doi.org/10.1145/3299874.3318030This work investigates if temperature can be used to fingerprint FPGA designs and presents a method to generate a large number of functionally equivalent FPGA designs such that each design has a unique distinguishable thermal signature. The main ...
- panelFebruary 2019
FPGAs in Supercomputers: Opportunity or Folly?
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 201https://doi.org/10.1145/3289602.3293929Supercomputers play an important role in the field of computational science, and are used for a wide range of computationally intensive tasks in various fields. So far, the building blocks for supercomputers have been dominated by CPUs and GPUs. ...
- research-articleFebruary 2019
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPages 262–271https://doi.org/10.1145/3289602.3293909In this work we present a heterogeneous deployment stack, calledGalapagos, that includes the abstraction of individual nodes (FPGAsand CPUs), the communication protocols between nodes and theorchestration and connection of these nodes into clusters. The ...
- posterOctober 2018
Hardware Acceleration of Searchable Encryption
CCS '18: Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications SecurityPages 2201–2203https://doi.org/10.1145/3243734.3278509Searchable symmetric encryption (SSE) allows a client to outsource the storage of her data to an (untrusted) server in a private manner, while maintaining the ability to selectively search over it. A key feature of all existing SSE schemes is the ...
- posterFebruary 2018
BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only)
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 290https://doi.org/10.1145/3174243.3174977Placement is probably the most critical process in the FPGA design flow. The demand for high performance continues to increase, but existing placers are still faced with numerous challenges including very long runtime, poor scalability, and restricted ...
- posterFebruary 2018
Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only)
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPage 289https://doi.org/10.1145/3174243.3174974Serial equivalency can provide easier regression testing and customer support in production-grade CAD software. While existing parallel routing techniques have become sufficiently advanced to accelerate the execution time, support for serial equivalency ...
- research-articleMarch 2017
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
ISPD '17: Proceedings of the 2017 ACM on International Symposium on Physical DesignPages 151–157https://doi.org/10.1145/3036669.3036682In this paper, we propose a new timing-driven detailed placement technique for FPGAs based on optimizing critical paths. Our approach extends well beyond the previously known critical path optimization approaches and explores a significantly larger ...