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- short-paperMay 2015
A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling
GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSIPages 367–372https://doi.org/10.1145/2742060.2742073Temperature is one of the major sources of delay variations which may cause timing violations. In this paper, an approach to temperature aware clock skew scheduling for a general class of sequential circuits is proposed. At first, an alternative ...
- posterMay 2014
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]
GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSIPages 91–92https://doi.org/10.1145/2591513.2591571Post-Silicon clock-Skew Tuning (PSST) is a promising technology for improving performance-yield of VLSIs under process variations. On the other hand, the resultant circuit after PSST should be also robust for run-time timing variations due to the change ...
- ArticleJanuary 2014
Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits
VLSID '14: Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded SystemsPages 393–398https://doi.org/10.1109/VLSID.2014.74Carbon Nanotube Field Effect Transistors (CNTFETs) are attractive alternatives to MOSFET devices as CNTFETs benefit from higher on-current, better gate control and faster switching response. However CNTFET-based technologies suffer from higher process ...
- research-articleOctober 2012
On-chip measurement system for within-die delay variation of individual standard cells in 65-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (ITVL), Volume 20, Issue 10Pages 1876–1880https://doi.org/10.1109/TVLSI.2011.2162257New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and ...
- ArticleJune 2011
Tabu Search Algorithm for Core Selection in Multicast Routing
With the development of network multimedia technology, more and more real-time multimedia applications need to transmit information using multicast. The basis of multicast data transmission is to construct a multicast tree. The main problem concerning ...
- ArticleOctober 2009
Minimizing Routing Delay Variation in Case of Mobility
WIMOB '09: Proceedings of the 2009 IEEE International Conference on Wireless and Mobile Computing, Networking and CommunicationsPages 370–375https://doi.org/10.1109/WiMob.2009.69One of the main challenges in all-IP networks is the development of suitable mobility solution. Mobile IP (MIP) presents the standard protocol used to support IP mobility. However, MIP is inadequate for real-time applications and inter-domain mobility (...
- research-articleAugust 2008
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation
ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & DesignPages 93–98https://doi.org/10.1145/1393921.1393947Traditionally, spare rows/columns have been used in two ways: either to replace too leaky cells to reduce leakage, or to substitute faulty cells to improve yield. In contrast, we first choose a higher threshold voltage (Vth) and/or gate-oxide thickness (...
- articleApril 2008
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (FECCS), Volume E91-A, Issue 4Pages 1044–1053https://doi.org/10.1093/ietfec/e91-a.4.1044As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI. In this paper, we propose a novel class of robustness for a datapath against delay variations, which is named structural robustness against delay variation (...
- research-articleAugust 2007
End-to-end one-way delay estimation using one-way delay variation and round-trip time
QSHINE '07: The Fourth International Conference on Heterogeneous Networking for Quality, Reliability, Security and Robustness & WorkshopsArticle No.: 19, Pages 1–8https://doi.org/10.1145/1577222.1577249QoS-support technology in networks is based on measuring QoS metrics which reflect a magnitude of stability and performance such as delay, delay variation, available bandwidth and packet error rate and so on. The measurement of one-way delay essentially ...
- articleDecember 2006
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation*This study is a part of results in JEITA EDA technical special committee.
- Toshiki Kanamoto,
- Shigekiyo Akutsu,
- Tamiyo Nakabayashi,
- Takahiro Ichinomiya,
- Koutaro Hachiya,
- Atsushi Kurokawa,
- Hiroshi Ishikawa,
- Sakae Muromoto,
- Hiroyuki Kobayashi,
- Masanori Hashimoto
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (FECCS), Volume E89-A, Issue 12Pages 3666–3670https://doi.org/10.1093/ietfec/e89-a.12.3666In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error ...
- articleDecember 2006
Design Method of High Performance and Low Power Functional Units Considering Delay Variations
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (FECCS), Volume E89-A, Issue 12Pages 3519–3528https://doi.org/10.1093/ietfec/e89-a.12.3519As VLSI technology advances, delay variations will become more serious. Delay-insensitive asynchronous dual-rail circuits tolerate any delay variation, but their energy consumption is more than double that of the single-rail circuits because signal ...
- articleMarch 2005
Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay
Analog Integrated Circuits and Signal Processing (KLU-ALOG), Volume 42, Issue 3Pages 209–217https://doi.org/10.1007/s10470-005-6755-8A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip wire delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The ...
- ArticleJune 2004
Re-synthesis for delay variation tolerance
DAC '04: Proceedings of the 41st annual Design Automation ConferencePages 814–819https://doi.org/10.1145/996566.996785Several factors such as process variation, noises, and delay defects can degrade the reliabilities of a circuit. Traditional methods add a pessimistic timing margin to resolve delay variation problems. In this paper, instead of sacrificing the ...
- ArticleNovember 2002
Active probing using packet quartets
IMW '02: Proceedings of the 2nd ACM SIGCOMM Workshop on Internet measurmentPages 293–305https://doi.org/10.1145/637201.637247A significant proportion of link bandwidth measurement methods are based on IP's ability to control the number of hops a packet can traverse along a route via the time-to-live (TTL) field of the IP header. A new delay variation based path model is ...
- ArticleAugust 2002
An efficient distributed multicast routing protocol with delay and delay variation constraints
Multicast routing consists of a tree which is rooted at the source node and contains all the multicast destinations. We study the problem of constructing a multicast tree that satisfies end-to-end delay along the paths from the source to each ...
- ArticleOctober 1997
Time-stamped transition density for the estimation of delay dependent switching activities
We propose a new method to improve the accuracy of the transition density for the estimation of delay dependent switching activities in combinational circuits. In the previous method, glitching sensitivity concept was defined and used to modify the ...
- ArticleJanuary 1997
Performance Comparison of Control Schemes for ABR Service in ATM LANs
The ATM Forum has defined a new service category, called the available bit rate service (ABR), which is intended for applications requiring tightly constrained cell loss but no bound on the delay or delay variation. Appropriate traffic control schemes ...
- ArticleOctober 1996
Performance analysis of a Banyan based ATM switching fabric with packet priority
We propose a new model for the performance analysis of an ATM switching fabric based on a single-buffered Banyan network. In this model, we use a three-state, i.e., "empty", "new" and "blocked" Markov chain model to describe the behavior of the buffer ...