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- articleMay 2009
A complexity-effective microprocessor design with decoupled dispatch queues and prefetching
Parallel Computing (PACO), Volume 35, Issue 5Pages 255–268https://doi.org/10.1016/j.parco.2008.12.008Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues (or centralized reservation stations) in modern superscalar microprocessors. However, such large dispatch queues are inevitably accompanied by high ...
- ArticleApril 2003
HiDISC: A Decoupled Architecture for Data-Intensive Applications
IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed ProcessingPage 3.2This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching ...
- ArticleDecember 1995
Compiling and optimizing for decoupled architectures
Supercomputing '95: Proceedings of the 1995 ACM/IEEE conference on SupercomputingPages 40–eshttps://doi.org/10.1145/224170.224301Decoupled architectures provide a key to the problem of sustained supercomputer performance through their ability to hide large memory latencies. When a program executes in a decoupled mode the perceived memory latency at the processor is zero; ...