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Compiling and Optimizing for Decoupled Architectures

Nigel Topham (1)
e-mail: npt@dcs.ed.ac.uk

Alasdair Rawsthorne(2)
e-mail: alasdair@cs.man.ac.uk

Callum McLean(1)
e-mail: callum@quadstone.co.uk

Muriel Mewissen(1)
e-mail: mu@quadstone.co.uk

Peter Bird(3)
e-mail: plbird@aol.com

(1) Department of Computer Science
The University of Edinburgh
Mayfield Road
Edinburgh, UK

(2) Department of Computer Science
The University of Manchester
Oxford Road
Manchester, UK

(3) Department of Computer Science
The University of Michigan

© Copyright 1995 by ACM, Inc.

Keywords

Decoupled architecture, Compiling, Performance, Benchmarks, Optimization, Quantitative analysis.

Abstract

Decoupled architectures provide a key to the problem of sustained supercomputer performance through their ability to hide large memory latencies. When a program executes in a decoupled mode the perceived memory latency at the processor is zero; effectively the entire physical memory has an access time equivalent to the processor's register file, and latency is completely hidden. However, the asynchronous functional units within a decoupled architecture must occasionally synchronize, incurring a high penalty. The goal of compiling and optimizing for decoupled architectures is to partition the program between the asynchronous functional units in such a way that latencies are hidden but synchronization events are executed infrequently. This paper describes a model for decoupled compilation, and explains the effectiveness of compilation for decoupled systems. A number of new compiler optimizations are introduced and evaluated quantitatively using the Perfect Club scientific benchmarks. We show that with a suitable repertiore of optimizations, it is possible to hide large latencies most of the time for most of the programs in the Perfect Club.

• Contents
• 1. Introduction
  • 1.1 Overview of decoupled architecture
• 2. A Compilation Model for Decoupled Architectures
  • 2.1 The target architecture
  • 2.2 A dynamic execution model for decoupled architectures
  • 2.3 The experimental compiler
  • 2.4 Causes of loss of decoupling
  • 2.5 Placement of LOD events
• 3. Compiler Effectiveness
  • 3.1 Cost model for decoupled execution
  • 3.2 LOD frequencies in the Perfect Club
  • 3.3 Effect of LOD placement
• 4. Idiomatic Transformations
  • 4.1 Pre-queueing for indirect accesses
  • 4.2 Loop distribution for computed indices
  • 4.3 IF-conversion
  • 4.4 Subroutine inlining
  • 4.5 Speculative loop dispatch
• 5. Conclusions
• References
• A. Dominant LOD points in the Perfect Club
  • A.1 Examples of IF-conversion in the Perfect Club
  • A.2 Example of inline decoupling of intrinsics
  • A.3 Potential for improved decoupling
  • A.4 Robust hoisting
  • A.5 The Effect of Subroutine Calls
  • A.6 Difficult LODs
• B. LOD Locality in the Perfect Club
• C. Acknowledgements
• About this document ...

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