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A new approach, using iddq, for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while ...

The advantage of random testing is that test application can be performed a t a low cost in the BIST scheme. However, not all circuits are random patter n testable. In this paper, we present a method for improving random pattern testability of logic ...

This paper presents a test generation method for sequential circuits assuming IDDQ testing. We consider external bridging faults and internal bridging faults as a target fault. Test generation for external bridging faults consists of three phases as 1) ...

Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with IDDQ testing. In this article we propose two IDDQ test able PLA configurations. In these configurations adjacent precharge lines (and ...

This paper introduces a test method for analogue (parts of) ICs that determines whether an IC is good or not by measuring the currents flowing through its constituent circuits. The ICCQ test method is not a full functional test. It is aimed primarily at ...

A design for test method for improving dynamic supply current testing reliability on regenerative sense amplifier structures is described in this paper. This proposal uses a built-in current monitor to represent the supply current trough the ...

The success of Iddq testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of ...

As device dimensions approach 0.1 /spl mu/m, analog effects will play an even larger role in digital circuits. IDDQ measurements can be significantly affected by the observed wafer to wafer (and even die to die) variations in electrical parameters. In ...

The Hewlett-Packard PA7300LC is a 180 MHz PA-RISC microprocessor consisting of 1.2 million core logic transistors and 8 million cache transistors. The design of the power distribution network for this chip allowed independent measurement of the I/sub ...

Sandia is manufacturing high reliability CMOS ICs with a 0.5 micron CMP technology, as part of the progression to 0.35 micron and smaller scale technologies. To qualify this technology for delivery of high reliability ICs to customers for military, ...

An efficient algorithm, named state transition based method (STEM), for simulating I/sub DDQ/ tests for leakage faults is presented. It also provides an efficient framework for "incremental fault simulation" which is embedded in the problem of selecting ...

In this paper we propose a new hybrid (logic+I/sub DDQ/) testing strategy for efficient bridging fault (BF) detection. In our strategy, logic and I/sub DDQ/ testings are applied in sequence so that BFs that can be detected by the logic testing need not ...

I/sub DDQ/ testing of CMOS circuits can detect faults that are not easily detected using traditional test techniques. The quiescent current drawn by CMOS devices is very small, and certain faults in a device may cause this current to increase by several ...

A new approach for the detection of bridging fault-induced delay faults in static CMOS logic circuits is presented in this paper. It is based upon the transient current that is sourced (or sink) by the power supply (or ground) rail of a primary output ...

This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifies transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the ...

A CMOS built-in current sensor is proposed. It is dedicated to mixed signal circuits power supply current monitoring. It takes advantage of a parasitic resistor, so its implementation is very transparent. Measurement results of a manufactured test chip ...

This paper presents a high-speed low-voltage built-in current sensor. It mainly utilizes a bulk-driven current mirror as a current sensor to reduce the power supply voltage drop. Based on this technique, we develop an analytic and empirical model to ...

IDDQ measurements are strongly identified with CMOS IC testing, however IDDQ also has long term links to IC reliability. This paper overviews the association of reliability and IDDQ testing. Three reliability topics are discussed: fundamental failure ...

New methods for detecting bridging faults in dynamic CMOS circuits are proposed. We show that resistive shorts in CMOS dynamic circuits can cause intermittent failures and reliability problems. We found that the defect coverage of resistive shorts, ...

In this paper, a supply current sensing circuit for detecting feedback bridging faults, which generate oscillation when a sensitized input is provided, is proposed. The circuit consists of an I-V transformer, a high frequency amplifier and a ...

Logic circuits in the presence of resistive shorts often exhibit analog behavior which can be computationally expensive to simulate. This paper introduces a numerical method called simplicial approximation for its application to simulation of logic/IDDQ ...