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10.5555/646847guideproceedingsBook PagePublication PagesConference Proceedingsacm-pubtype
FTRTFT '02: Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
2002 Proceeding
Publisher:
  • Springer-Verlag
  • Berlin, Heidelberg
Conference:
September 9 - 12, 2002
ISBN:
978-3-540-44165-6
Published:
09 September 2002

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Abstract

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Article
UPPAAL Implementation Secrets
Pages 3–22

In this paper we present the continuous and on-going development of datastructures and algorithms underlying the verification engine of the tool UPPAAL. In particular, we review the datastructures of Difference Bounded Matrices, Minimal Constraint ...

Article
Software Hazard and Safety Analysis
Pages 23–36

Safety is a system property and software, of itself, cannot be safe or unsafe. However software has a major influence on safety in many modern systems, e.g. aircraft and engine controls, railway signalling, and medical equipment.The paper outlines the ...

Article
Real-Time Operating Systems: Problems and Novel Solutions
Pages 37–52

This work presents some methodologies for enhancing predictability in real-time computing systems, where explicit timing constraints have to be enforced on application processes. In order to provide an off-line guarantee of the critical timing ...

Article
Real-Time UML
Pages 53–70

The UML (Unified Modeling Language) is a third-generation object-oriented modeling language recently accepted as a standard by the OMG (Object Management Group). The OMG is an association of over 800 leading technology companies that have banded ...

Article
Eager Class Initialization for Java
Pages 71–80

We describe a static analysis method on Java bytecode to determine class initialization dependencies. This method can be used for eager class loading and initialization. It catches many initialization circularities that are missed by the standard lazy ...

Article
Applications of Formal Methods in Biology
Pages 81–82

From the first introduction of the notion of "Reactive Systems" and development of specification languages (such as Temporal Logic and Statecharts) and verification methods for this class of systems, it has been stated that this notion encompasses a ...

Article
An Overview of Formal Verification for the Time-Triggered Architecture
Pages 83–106

We describe formal verification of some of the key algorithms in the Time-Triggered Architecture (TTA) for real-time safety-critical control applications. Some of these algorithms pose formidable challenges to current techniques and have been formally ...

Article
Scheduler Modeling Based on the Controller Synthesis Paradigm
Pages 107–110

The controller synthesis paradigm provides a general framework for scheduling real-time applications. Schedulers can be considered as controllers of the applications; they restrict their behavior so that given scheduling requirements are met.We study a ...

Article
Component-Based Synthesis of Dependable Embedded Software
Pages 111–128

Standardized and reusable software (SW) objects (or SW components - in-house or pre-fabricated) are increasingly being used to reduce the cost of software (SW) development. Given that the basic components may not have been developed with dependability ...

Article
From the Specification to the Scheduling of Time-Dependent Systems
Pages 129–146

This paper introduces and formalizes a new variant of Timed Automata, called Time Labeled Scheduling Automata. A Time Labeled Scheduling Automaton is a single clock implementation model expressing globally the time constraints that a system has to meet. ...

Article
On Control with Bounded Computational Resources
Pages 147–164

We propose models that capture the influence of computation on the performance of computer-controlled systems, and make it possible to employ computational considerations in early stages of the design process of such systems. The problem of whether it ...

Article
Decidability of Safety Properties of Timed Multiset Rewriting
Pages 165–184

We propose timed multiset rewriting as a framework that subsumes timed Petri nets and timed automata. In timed multiset rewriting, which extends multiset rewriting, each element of a multiset has a clock, and a multiset is transformed not only by usual ...

Article
Extending Timed Automaton and Real-Time Logic to Many-Valued Reasoning
Pages 185–204

Past decade has witnessed a great advance in the field of dense-time formal methods for the specification, synthesis and analysis of real time systems. In this context timed automata and real-time temporal logics provide a simple, and yet general, way ...

Article
Fault Diagnosis for Timed Automata
Pages 205–224

We study the problem of fault-diagnosis in the context of dense-time automata. The problem is, given the model of a plant as a timed automaton with a set of observable events and a set of unobservable events, including a special event modeling faults, ...

Article
Verification of Timed Automata via Satisfiability Checking
Pages 225–244

In this paper we show how to translate bounded-length verification problems for timed automata into formulae in difference logic, a propositional logic enriched with timing constraints. We describe the principles of a satisfiability checker specialized ...

Article
Take It NP-Easy: Bounded Model Construction for Duration Calculus
Pages 245–264

Following the recent successes of bounded model-checking, we reconsider the problem of constructing models of discrete-time Duration Calculus formulae. While this problem is known to be nonelementary when arbitrary length models are considered [Han94], ...

Article
Towards Bounded Model Checking for the Universal Fragment of TCTL
Pages 265–290

Bounded Model Checking (BMC) based on SAT methods consists in searching for a counterexample of a particular length and to generate a propositional formula that is satisfiable iff such a counterexample exists. Our paper shows how the concept of bounded ...

Article
A Typed Interrupt Calculus
Pages 291–310

Most real-time systems require responsive interrupt handling. Programming of interrupt handlers is challenging: in order to ensure responsiveness, it is often necessary to have interrupt processing enabled in the body of lower priority handlers. It ...

Article
Parametric Verification of a Group Membership Algorithm
Pages 311–330

We address the problem of verifying clique avoidance in the TTP protocol. TTP allows several stations embedded in a car to communicate. It has many mechanisms to ensure robustness to faults. In particular, it has an algorithm that allows a station to ...

Article
A Method for Testing the Conformance of Real Time Systems
Pages 331–354

The aim of conformance testing is to check whether an implementation conforms to a specification. We consider the case where the specification contains timing constraints and is described by a model called Timed Automata (TA). The state space of a TA ...

Article
A Probabilistic Extension of UML Statecharts
Pages 355–374

This paper introduces means to specify system randomness within UML statecharts, and to verify probabilistic temporal properties over such enhanced statecharts which we call probabilistic UML statecharts. To achieve this, we develop a general recipe to ...

Article
Eliminating Queues from RT UML Model Representations
Pages 375–394

This paper concerns analyzing UML based models of distributed real time systems involving multiple active agents. In order to avoid the time-penalties incurred by distributed execution of synchronous operation calls, it is typically recommended to ...

Article
Model Checking - Timed UML State Machines and Collaborations
Pages 395–416

We describe a prototype tool, HUGO/RT, that is designed to automatically verify whether the timed state machines in a UML model interact according to scenarios specified by time-annotated UML collaborations. Timed state machines are compiled into timed ...

Article
Partial Order Path Technique for Checking Parallel Timed Automata
Pages 417–432

In a parallel composition of timed automata, some transitions are independent to others. Generally the basic method generates one successors for each of the legal permutations of the transitions. These successors may be combined into one bigger symbolic ...

Article
Constructing Test Automata from Graphical Real-Time Requirements
Pages 433–454

A semantics for a graphical specification language of real-time properties (Constraint Diagrams) is presented. The new semantics is given in terms of Timed Automata. A model in terms of Timed Automata satisfies the property given by a Constraint Diagram ...

Contributors
  • University of Oldenburg
  • University of Oldenburg
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