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Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications

Authors:

Madhumitha Ravichandran,

Nathan ClarkAuthors Info & Claims

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

Pages 270 - 279

https://doi.org/10.1145/1815961.1815996

Published: 19 June 2010 Publication History

Abstract

Extracting performance from modern parallel architectures requires that applications be divided into many different threads of execution. Unfortunately selecting the appropriate number of threads for an application is a daunting task. Having too many threads can quickly saturate shared resources, such as cache capacity or memory bandwidth, thus degrading performance. On the other hand, having too few threads makes inefficient use of the resources available. Beyond static resource assignment, the program inputs and dynamic system state (e.g., what other applications are executing in the system) can have a significant impact on the right number of threads to use for a particular application.

To address this problem we present the Thread Tailor, a dynamic system that automatically adjusts the number of threads in an application to optimize system efficiency. The Thread Tailor leverages offline analysis to estimate what type of threads will exist at runtime and the communication patterns between them. Using this information Thread Tailor dynamically combines threads to better suit the needs of the target system. Thread Tailor adjusts not only to the architecture, but also other applications in the system, and this paper demonstrates that this type of adjustment can lead to significantly better use of thread-level parallelism in real-world architectures.

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Cited By

Knorst TJordan MKorol GRutzig MBeck A(2024)An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning2024 XIV Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC65055.2024.10771920(1-6)Online publication date: 26-Nov-2024
https://doi.org/10.1109/SBESC65055.2024.10771920
Moori MRocha HLorenzon ABeck A(2024)Efficient Thread Tuning for Asymmetric Multicores2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI62366.2024.10703981(1-5)Online publication date: 2-Sep-2024
https://doi.org/10.1109/SBCCI62366.2024.10703981
Schwarzrock JLorenzon Ade Souza SBeck A(2024)Integration Framework for Online Thread Throttling with Thread and Page Mapping on NUMA Systems2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00202(1189-1192)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00202
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Index Terms

Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications
1. Computer systems organization
  1. Architectures
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Dynamic compilers
      2. Runtime environments
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management

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Published In

cover image ACM Conferences

ISCA '10: Proceedings of the 37th annual international symposium on Computer architecture

June 2010

520 pages

ISBN:9781450300537

DOI:10.1145/1815961

General Chair:
André Seznec
INRIA Rennes
,
Program Chairs:
Uri Weiser
Technion
,
Ronny Ronen
Intel

ACM SIGARCH Computer Architecture News Volume 38, Issue 3
ISCA '10
June 2010
508 pages
ISSN:0163-5964
DOI:10.1145/1816038
Issue’s Table of Contents

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 June 2010

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ISCA '10: The 37th Annual International Symposium on Computer Architecture

June 19 - 23, 2010

Saint-Malo, France

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Knorst TJordan MKorol GRutzig MBeck A(2024)An Automatic Framework for Collaborative CPU Thread Throttling and FPGA HLS-Versioning2024 XIV Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC65055.2024.10771920(1-6)Online publication date: 26-Nov-2024
https://doi.org/10.1109/SBESC65055.2024.10771920
Moori MRocha HLorenzon ABeck A(2024)Efficient Thread Tuning for Asymmetric Multicores2024 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI62366.2024.10703981(1-5)Online publication date: 2-Sep-2024
https://doi.org/10.1109/SBCCI62366.2024.10703981
Schwarzrock JLorenzon Ade Souza SBeck A(2024)Integration Framework for Online Thread Throttling with Thread and Page Mapping on NUMA Systems2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00202(1189-1192)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00202
Huang HZhao YRao JWu SJin HWang DKun SPan L(2023)Adapt Burstable Containers to Variable CPU ResourcesIEEE Transactions on Computers10.1109/TC.2022.317448072:3(614-626)Online publication date: 1-Mar-2023
https://doi.org/10.1109/TC.2022.3174480
Moori MRocha HLorenzon ABeck A(2023)Searching for the Ideal Number of Threads on Asymmetric Multiprocessors2023 XIII Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC60926.2023.10324167(1-6)Online publication date: 21-Nov-2023
https://doi.org/10.1109/SBESC60926.2023.10324167
Luan GPang PChen QXue SSong ZGuo M(2022)Online Thread Auto-Tuning for Performance Improvement and Resource SavingIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.316941033:12(3746-3759)Online publication date: 1-Dec-2022
https://doi.org/10.1109/TPDS.2022.3169410
Knorst TKorol GJordan MVicenzi JLorenzon ARutzig MBeck A(2022)On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI55532.2022.9893223(1-6)Online publication date: 22-Aug-2022
https://doi.org/10.1109/SBCCI55532.2022.9893223
Huang HRao JWu SJin HJiang HChe HWu XLaure EMarkidis SVerbanescu ALofstead G(2021)Towards Exploiting CPU Elasticity via Efficient Thread OversubscriptionProceedings of the 30th International Symposium on High-Performance Parallel and Distributed Computing10.1145/3431379.3460641(215-226)Online publication date: 21-Jun-2021
https://dl.acm.org/doi/10.1145/3431379.3460641
Knorst TJordan MLorenzen ARutzig MSchneider Beck A(2021)ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI53441.2021.9529986(1-6)Online publication date: 23-Aug-2021
https://doi.org/10.1109/SBCCI53441.2021.9529986
Marques SMedeiros TSerpa MRossi FLuizelli MNavaux PBeck ALorenzon A(2021)Optimizing Parallel Applications via Dynamic Concurrency Throttling and Turbo Boosting2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP52278.2021.00032(153-160)Online publication date: Mar-2021
https://doi.org/10.1109/PDP52278.2021.00032
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