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Geyser-2: the second prototype CPU with fine-grained run-time power gating

Published: 25 January 2011 Publication History

Abstract

Geyser-2 is the second prototype MIPS CPU which provides a fine-grained run-time power gating (PG) controlled by instructions. Geyser-1[1], the first prototype only provides the fine-grained run-time PG core. Although it demonstrated the leakage power reduction on a real chip, the operational frequency is limited at 60MHz because of the limitation of the I/O speed. Geyser-2 with cache and TLB mechanism is implemented to show (1) run-time PG works at least with 200MHz which is commonly used clock for embedded systems, and (2) it is also efficient on the environment with real application programs with an operating system.

References

[1]
D. Ikebuchi and et.al., "Geyser-1: A mips r3000 cpu core with fine grain runtime power gating," ASSCC 2009, 2009.
[2]
N. K. Usami, "An approach for fine-grained run-time power gating using locally extracted sleep signals," ICCD, Oct. 2006.
[3]
I. Sequence Design, "Cool power," www.sequencedesign.com.
[4]
N. Seki and et.al., "A Fine Grain Dynamic Sleep Control Scheme in MIPS R3000," ICCD 2008, 2008.
[5]
E. Farquhar and P. Bunce, THE MIPS PROGRAMMER'S HANDBOOK. Morgan Kaufmann Publishers, 1994.

Cited By

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  • (2014)Design and evaluation of fine-grained power-gating for embedded microprocessorsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616785(1-6)Online publication date: 24-Mar-2014

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cover image ACM Conferences
ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference
January 2011
841 pages
ISBN:9781424475162

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IEEE Press

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Published: 25 January 2011

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  • (2014)Design and evaluation of fine-grained power-gating for embedded microprocessorsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616785(1-6)Online publication date: 24-Mar-2014

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