research-article

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

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Ching-Hwa ChengAuthors Info & Claims

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

Pages 73 - 74

Published: 25 January 2011 Publication History

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Abstract

This paper proposes a dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width. A design automation environment for simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 um CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.

References

[1]

C. D. Chien, et. al., "A 252K Gates/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications," ISSCC Dig. Tech. Papers, pp. 282--283, 2007.

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T. M. Liu, et. al., "A 125μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 402--403, 2006.

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[3]

FUJITSI MB86H60 FACTSHEET, "HD Multi-Standard Decoder," May 2008, <http://www.fujitsu.com/downloads/MICRO/fme/mpeg/multimedia/mb86h60_factsheet.pdf>.

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Silicon Image MSVD-HD Product Brief, "Multi-Standard High-Definition Video Decoder," March 2007, <http://www.siliconimage.com/docs/MSVD_pb_FINAL_3-28-07.pdf>.

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ASTRI Product Brief, "H.264 High Profile Video Decoder," 2008, <http://www.astri.org/en/ece06k_mst_h264decoder.php>.

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FULHAN Product Brief, "FH8602 H.264 HD Decoder," Nov. 2006, <http://www.fullhan.com/images/8602.pdf>.

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Heiko Schwarz, et al., "Overview of the scalable video coding extension of the H.264/AVC standard," IEEE Trans. Circuits Syst. Video Technol., pp. 1103--1120, Sep. 2007.

Digital Library

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[8]

C. A. Chien, et. al., "A 39K Gates/10.9KB SRAM/2-328 mW Dual Mode Video Decoder Supporting Temporal/Spatial Scalable Video," ASSCC Dig. Tech. Papers, pp. 197--200, 2009.

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A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video

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Information & Contributors

Information

Published In

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

January 2011

841 pages

ISBN:9781424475162

Publisher

IEEE Press

Publication History

Published: 25 January 2011

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Research-article

Conference

ASPDAC '11

Sponsor:

SIGDA
IEICE ESS

ASPDAC '11: 16th Asia and South Pacific Design Automation Conference

January 25 - 28, 2011

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Resistorless dual-mode quadrature sinusoidal oscillator using a single active building block