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A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial parts

Authors:

Luca DanielAuthors Info & Claims

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

Pages 49 - 54

Published: 25 January 2011 Publication History

Abstract

Passivity-preserving model order reduction (MOR) of descriptor systems (DSs) is highly desired in the simulation of VLSI interconnects and on-chip passives. One popular method is PRIMA, a Krylov-subspace projection approach which preserves the passivity of positive semidefinite (PSD) structured DSs. However, system passivity is not guaranteed by PRIMA when the system is indefinite. Furthermore, the possible polynomial parts of singular systems are normally not captured. For indefinite DSs, positive-real balanced truncation (PRBT) can generate passive reduced-order models (ROMs), whose main bottleneck lies in solving the dual expensive generalized algebraic Riccati equations (GAREs). This paper presents a novel moment-matching MOR for indefinite DSs, which preserves both the system passivity and, if present, also the improper polynomial part. This method only requires solving one GARE, therefore it is cheaper than existing PRBT schemes. On the other hand, the proposed algorithm is capable of preserving the passivity of indefinite DSs, which is not guaranteed by traditional moment-matching MORs. Examples are finally presented showing that our method is superior to PRIMA in terms of accuracy.

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Cited By

Vasudevan VRamakrishna M(2015)An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor formProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744770(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744770

Index Terms

A moment-matching scheme for the passivity-preserving model order reduction of indefinite descriptor systems with possible polynomial parts
1. Hardware

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cover image ACM Conferences

ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

January 2011

841 pages

ISBN:9781424475162

Sponsors

IEEE
IPSJ
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEICE

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IEEE Press

Publication History

Published: 25 January 2011

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ASPDAC '11

Sponsor:

SIGDA
IEICE ESS

ASPDAC '11: 16th Asia and South Pacific Design Automation Conference

January 25 - 28, 2011

Yokohama, Japan

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Cited By

Vasudevan VRamakrishna M(2015)An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor formProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744770(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744770

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