Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems

To achieve high efficiency and prevent destructive interference among multiple divergent workloads, the last-level cache of Chip Multiprocessors has to be carefully managed. Previously proposed cache management schemes suffer from inefficient cache capacity utilization, by either focusing on improving the absolute number of cache misses or by allocating cache capacity without taking into consideration the applications’ memory sharing characteristics. Reduction of the overall number of misses does not always correlate with higher performance as Memory-level Parallelism can hide the latency penalty of a significant number of misses in out-of-order execution. In this work we describe a quasi-partitioning scheme for last-level caches that combines the memory-level parallelism, cache friendliness and interference sensitivity of competing applications, to efficiently manage the shared cache capacity. The proposed scheme improves both system throughput and execution fairness—outperforming previous schemes that are oblivious to applications’ memory behavior. Our detailed, full-system simulations showed an average improvement of 10 percent in throughput and 9 percent in fairness over the next best scheme for a four-core CMP system.