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- Muramatsu AHashimoto MOnodera HGroeneveld PScheffer L(2005)Effects of on-chip inductance on power distribution gridProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055152(63-69)Online publication date: 3-Apr-2005
- Singh APatel CPlusquellic J(2004)Fault Simulation Model for i{DDT} TestingProceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987946Online publication date: 25-Apr-2004