More Web Proxy on the site http://driver.im/

article

IBM POWER6 microprocessor physical design and design methodology

IBM Journal of Research and Development, Volume 51, Issue 6

Pages 685 - 714

https://doi.org/10.1147/rd.516.0685

Published: 01 November 2007 Publication History

Abstract

The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

References

[1]

1. E. Leobandung, E. Nayakama, H. Mocuta, D. Miyamoto, K. Angyal, M. Meer, H. V. McStay, et al., "High Performance 65 nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM Cell," 2005 Symposium on VLSI Technology, Digest of Technical Papers, June 14-16, 2005, pp. 126-127.

[2]

2. J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson, "The Circuit and Physical Design of the POWER4 Microprocessor," IBM J. Res. & Dev. 46, No. 1, pp. 27-51 (2002).

Digital Library

[3]

3. B. W. Curran, Y. H. Chan, P. T. Wu, P. J. Camporese, G. A. Northrop, R. F. Hatch, L. B. Lacey, J. P. Eckhardt, D. T. Hui, and H. H. Smith, "IBM eServer z900 High-Frequency Microprocessor Technology, Circuits, and Design Methodology," IBM J. Res. & Dev. 46, No. 4/5, pp. 631-644 (2002).

Digital Library

[4]

4. V. Rao, J. Soreff, T. Brodnax, and R. Mains, "EinsTLT: Transistor Level Timing with EinsTimer," Proceedings of the International Workshop on Timing Issues (TAU) in the Specification and Synthesis of Digital Systems, March 8-9, 1999, pp. 1-6.

[5]

5. A. R. Conn, K. Scheinberg, and Ph. L. Toint, "A Derivative Free Optimization Algorithm in Practice," Proceedings of the 7th AIAA/USAF/NASA/ISSMO Symposium on Multidisciplinary Analysis and Optimization, St. Louis, MO, 1998.

[6]

6. P. J. Camporese, A. Deutsch, T. G. McNamara, P. Restle, and D. Webber, "X-Y Grid Tree Tuning Method," U.S. Patent No. 6,205,571, March 20, 2001.

[7]

7. P. J. Restle, R. L. Franch, N. K. Norman, W. V. Huott, T. M. Skergan, S. C. Wilson, N. S. Schwartz, and J. G. Clabes, "Timing Uncertainty Measurements on the POWER5 Microprocessor," 2004 IEEE International Solid-States Circuits Conference, Digest of Technical Papers, February 15-19, 2004, pp. 354-355.

[8]

8. M. S. Floyd, S. Ghiasi, T. W. Keller, K. Rajamani, F. L. Rawson, J. C. Rubio, and M. S. Ware, "System Power Management Support in the IBM POWER6 Microprocessor," IBM J. Res. & Dev. 51, No. 6, pp. 733-746 (2007, this issue).

Digital Library

[9]

9. S. R. Nassif and J. N. Kozhaya, "Fast Power Grid Simulation," Proceedings of the 37th Design Automation Conference, 2000, pp. 156-161.

[10]

10. J. S. Neely, H. H. Chen, S. G. Walker, J. Venuto, and T. J. Bucelot, "CPAM: A Common Power Analysis Methodology for High-Performance VLSI Design," IEEE Conference on Electrical Performance of Electronic Packaging, Scottsdale, AZ, October 23-25, 2000, pp. 303-306.

[11]

11. R. M. Averill III, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Hoffman, et al., "Chip Integration Methodology for the IBM S/390 G5 and G6 Custom Microprocessors," IBM J. Res. & Dev. 43, No. 5/6, pp. 681-706 (1999).

[12]

12. H. Smith, A. Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, and B. Krauter, "R(f)L(f)C Coupled Noise Evaluation of an S/390 Microprocessor Chip," IEEE Conference on Custom Integrated Circuits, San Diego, May 2001, pp. 237-240.

[13]

13. A. Deutsch, H. H. Smith, B. J. Rubin, B. L. Krauter, and G. V. Kopcsay, "New Methodology for Combined Simulation of Delta-I Noise Interaction with Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power Blocks," IEEE Transactions on Advanced Packaging, Vol. 29, February 2006, pp. 11-20.

[14]

14. K. L. Shepard and V. Narayanan, "Noise in Deep Submicron Digital Design," 1996 International Conference on Computer-Aided Design (ICCAD 1996), Digest of Technical Papers, 1996, pp. 524-531.

[15]

15. J. R. Black, "Electromigration--A Brief Survey and Some Recent Results," IEEE Transactions on Electron Devices, Vol. 16, 1969, pp. 338-347.

[16]

16. J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., "Design of the POWER6 Microprocessor," Proceedings of the International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco, CA, February 11-15, 2007, pp. 96-97.

Cited By

Hossain MDesai CChen TAgarwal V(2015)Synthesis-based design and implementation methodology of high-speed, high-performing unitIntegration, the VLSI Journal10.1016/j.vlsi.2014.10.00149:C(125-136)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.10.001
Adler OArbel EAverbouch IBeer IGrijnevitch IFettweis GNebel W(2014)Facilitating timing debug by logic path correspondenceProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616989(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616989
Yang JLi ZCai YZhou QHu A(2012)PowerRushProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429526(653-659)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429526
Show More Cited By

Index Terms

IBM POWER6 microprocessor physical design and design methodology

Recommendations

Design and microarchitecture of the IBM system z10 microprocessor

The IBM System z10^™ microprocessor is currently the fastest running 64-bit CISC (complex instruction set computer) microprocessor. This microprocessor operates at 4.4 GHz and provides up to two times performance improvement compared with its predecessor,...
The IBM z13 multithreaded microprocessor

The IBM z13™ system is the latest generation of the IBM z Systems™ mainframes. The z13 microprocessor improves upon the IBM zEnterprise® EC12 (zEC12) processor with two vector execution units, higher instruction execution parallelism, and a simultaneous ...
Design methodology for the IBM POWER7 microprocessor

The IBM POWER7^® microprocessor, which is the next-generation IBM POWER^® processor, leverages IBM's 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex 567-...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image IBM Journal of Research and Development

IBM Journal of Research and Development Volume 51, Issue 6

November 2007

147 pages

ISSN:0018-8646

Issue’s Table of Contents

Publisher

IBM Corp.

United States

Publication History

Published: 01 November 2007

Accepted: 18 September 2007

Received: 01 February 2007

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 24 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Hossain MDesai CChen TAgarwal V(2015)Synthesis-based design and implementation methodology of high-speed, high-performing unitIntegration, the VLSI Journal10.1016/j.vlsi.2014.10.00149:C(125-136)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.10.001
Adler OArbel EAverbouch IBeer IGrijnevitch IFettweis GNebel W(2014)Facilitating timing debug by logic path correspondenceProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616989(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616989
Yang JLi ZCai YZhou QHu A(2012)PowerRushProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429526(653-659)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429526
Friedrich JPuri RBrandt UBuehler MDiLullo JHopkins JHossain MKazda MKeinert JKurzum ZLamb DLee AMusante FNoack JOsler PPosluszny SQian HRamji SRao VReddy LRen HRosser TRussell BSze CTéllez G(2011)Design methodology for the IBM POWER7 microprocessorIBM Journal of Research and Development10.1147/JRD.2011.210569255:3(294-307)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1147/JRD.2011.2105692
Chiang MOkamoto TYoshimura TBenini LDe Micheli GAl-Hashimi BMueller W(2009)Register placement for high-performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874972(1470-1475)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874972
Vratonjić MZiegler MGristede GZyuban VMitchell TCho EVisweswariah COklobdzija V(2009)A new methodology for power-aware transistor sizingProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_35(307-316)Online publication date: 9-Sep-2009
https://dl.acm.org/doi/10.1007/978-3-642-11802-9_35
Knickerbocker JAndry PDang BHorton RInterrante MPatel CPolastre RSakuma KSirdeshmukh RSprogis ESri-Jayantha SStephens ATopol ATsang CWebb BWright S(2008)Three-dimensional silicon integrationIBM Journal of Research and Development10.1147/JRD.2008.538856452:6(553-569)Online publication date: 1-Nov-2008
https://dl.acm.org/doi/10.1147/JRD.2008.5388564
Curran BFluhr EParedes JSigal LFriedrich JChan YHwang C(2007)Power-constrained high-frequency circuits for the IBM POWER6 microprocessorIBM Journal of Research and Development10.1147/rd.516.071551:6(715-731)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1147/rd.516.0715

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents