[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/981066.981074acmconferencesArticle/Chapter ViewAbstractPublication PagesispdConference Proceedingsconference-collections
Article

Multilevel routing with antenna avoidance

Published: 18 April 2004 Publication History

Abstract

As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits.

References

[1]
P. H. Chen, S. Malkani, C.-M. Peng, and J. Lin, "Fixing antenna problem by dynamic diode dropping and jumper insertion", Proc. International Symposium on Quality Electronic Design, pp 275--282, 2000.
[2]
Z. Chen and I. Koren, "Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing", Proc. Workshop on DFT, pp 77--85, 1996.
[3]
J. Cong, J. Fang, and Y. Zhang, "Multilevel approach to full-chip gridless routing", Proc. International Conference on CAD, pp. 396--403, Nov. 2001.
[4]
J. Cong, M. Xie, and Y. Zhang, "An enhanced multilevel routing system", Proc. International Conference on CAD, pp. 51--58, Nov. 2002.
[5]
J. Cong and J. Shinnerl, Multilevel Optimization in VLSICAD, Kluwer Academic Publishers, 2003.
[6]
H. T. Heineken, J. Khare, W. Maly, P. K. Nag, C. Ouyang, and W. A. Pleskacz, "CAD at the design-manufacturing interface", Proc. Design Automation Conference, pp. 321--326, Jun. 1997.
[7]
T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "A Fast Crosstalk- and Performance-Driven Multilevel Routing System", Proc. International Conference on CAD, pp.382--387, Nov. 2003.
[8]
L.-D. Huang, X. Tang, H. Xiang, D. F. Wong, and I.-M. Liu, "A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem", Proc. Design, Automation and Test in Europe, pp. 470--475, 2002.
[9]
A. B. Kahng, "Research directions for coevolution of rules and routers", Proc. International Symposium on Physical Design, pp. 122--125, Apr. 2003.
[10]
R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern routing: use and theory for increasing predictability and avoiding coupling", IEEE Trans. on CAD, pp. 777--790, Nov. 2002.
[11]
S. Krishnan, S. Rangan, S. Hattangady, G. Xing, K. Brennan, M. Rodder, and S. Ashok, "Assessment of charge-induced damage to ultra-thin gate MOSFETs", Proc. International Electron Devices Meeting, pp. 445--448, 1997.
[12]
H. K.-S. Leung, "Advanced routing in changing technology landscape", Proc. International Symposium on Physical Design, pp. 118--121, Apr. 2003.
[13]
S.-P. Lin and Y.-W. Chang, "A novel framework for multilevel routing considering routability and performance", Proc. International Conference on CAD, pp. 44--50, Nov. 2002.
[14]
W. Maly, C. Ouyang, S. Ghosh, and S. Maturi, "Detection of an antenna effect in VLSI designs", Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 86--94, Nov. 1996.
[15]
R. H. J. M. Otten, R. Camposano, and P. R. Groeneveld, "Design Automation for Deepsubmicron: present and future", Proc. Design, Automation and Test in Europe, pp. 650--657, 2002.
[16]
H. Shin, C.-C. King, and C. Hu, "Thin Oxide Damage by plasma etching and ashing process", Proc. International Reliability Physics Symposium, pp. 37--41, 1992.
[17]
H. Shirota, T. Sadakane, M. Terai, and K. Okazaki, "A new router for reducing "Antenna effect" in ASIC design", Proc. Custom Integrated Circuit Conference, pp. 27.5.1 -- 27.5.4, Sep. 1998.
[18]
K. P. Wang, M. Marek-Sadowska, and W. Maly, "Layout design for yield and reliability", Proc. Physical Design Workshop, pp. 190--197, Apr. 1996.
[19]
H. Watanabe, J. Komori, K. Higashitani, M. Sekine, and H. Koyama, "A wafer level monitoring method for plasma-charging damage using antenna PMOSFET test structure", IEEE Trans. on Semiconductor Manufacturing, pp. 228--232, May. 1997.

Cited By

View all
  • (2023)Restrictive antenna rules limiting PID degradation for MOS transistors with connected MIM-capacitors2023 IEEE International Integrated Reliability Workshop (IIRW)10.1109/IIRW59383.2023.10477710(1-6)Online publication date: 8-Oct-2023
  • (2016)RoutingElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-10(183-216)Online publication date: 14-Apr-2016
  • (2010)Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133495(312-318)Online publication date: 7-Nov-2010
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
ISPD '04: Proceedings of the 2004 international symposium on Physical design
April 2004
226 pages
ISBN:1581138172
DOI:10.1145/981066
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 April 2004

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. design for manufacturability (DFM)
  2. multilevel optimization
  3. nanometer
  4. physical design
  5. process antenna effect
  6. routing

Qualifiers

  • Article

Conference

ISPD04
Sponsor:
ISPD04: International Symposium on Physical Design 2004
April 18 - 21, 2004
Arizona, Phoenix, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25
International Symposium on Physical Design
March 16 - 19, 2025
Austin , TX , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)8
  • Downloads (Last 6 weeks)2
Reflects downloads up to 24 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2023)Restrictive antenna rules limiting PID degradation for MOS transistors with connected MIM-capacitors2023 IEEE International Integrated Reliability Workshop (IIRW)10.1109/IIRW59383.2023.10477710(1-6)Online publication date: 8-Oct-2023
  • (2016)RoutingElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-10(183-216)Online publication date: 14-Apr-2016
  • (2010)Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routingProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133495(312-318)Online publication date: 7-Nov-2010
  • (2010)Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5654184(312-318)Online publication date: Nov-2010
  • (2010)Routing's algorithms and considerations2010 IEEE International Conference on Electro/Information Technology10.1109/EIT.2010.5612108(1-4)Online publication date: May-2010
  • (2009)Routing for manufacturability and reliabilityIEEE Circuits and Systems Magazine10.1109/MCAS.2009.93385509:3(20-31)Online publication date: 1-Sep-2009
  • (2009)PIXARIntegration, the VLSI Journal10.1016/j.vlsi.2008.12.00242:3(400-408)Online publication date: 1-Jun-2009
  • (2009)A Performance-Driven Multilevel Framework for the X-Based Full-Chip RouterIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-95948-9_21(209-218)Online publication date: 2009
  • (2008)An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna FixingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.92324627:6(1055-1065)Online publication date: 1-Jun-2008
  • (2008)X-clock tree construction for antenna avoidance2008 9th International Conference on Solid-State and Integrated-Circuit Technology10.1109/ICSICT.2008.4735038(2248-2251)Online publication date: Oct-2008
  • Show More Cited By

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media