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Article

Using reconfigurability to achieve real-time profiling for hardware/software codesign

Authors:

Lesley Shannon,

Paul ChowAuthors Info & Claims

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Pages 190 - 199

https://doi.org/10.1145/968280.968308

Published: 22 February 2004 Publication History

Abstract

Embedded systems combine a processor with dedicated logic to meet design specifications at a reasonable cost. The attempt to amalgamate two distinct design environments introduces many problems, one being how to partition a single design for the two platforms to achieve the best performance with the least effort. Since the latest FPGA technology allows the integration of soft or hard CPU cores with dedicated logic on a single chip, this presents new opportunities for addressing hardware/software codesign issues in the FPGA design process by utilizing the reconfigurable environment.This paper introduces SnoopP, a non-intrusive, real time, profiling tool. The user is able to obtain a clock cycle accurate profile of the real time performance of a software program running on a soft-core processor instantiated on an FPGA. SnoopP is an essential tool for hardware/software codesign on a reconfigurable platform. It allows the user to quickly obtain accurate profiling information that may greatly influence the partitioning of the design.

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Cited By

Skordalakis EAttwood AGoodacre JLuján M(2024)AccProf: Increasing the Accuracy of Embedded Application Profiling Using FPGAsArchitecture of Computing Systems10.1007/978-3-031-66146-4_13(192-206)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-3-031-66146-4_13
Jaswal MRoy S(2022)DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path ProfilerIEEE Access10.1109/ACCESS.2022.321871010(116069-116086)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3218710
Dey MYilmaz BPrvulovic MZajic A(2021)PRIMER: Profiling Interrupts using Electromagnetic Side-Channel for Embedded DevicesIEEE Transactions on Computers10.1109/TC.2021.3109457(1-1)Online publication date: 2021
https://doi.org/10.1109/TC.2021.3109457
Show More Cited By

Index Terms

Using reconfigurability to achieve real-time profiling for hardware/software codesign
1. General and reference
  1. Cross-computing tools and techniques
    1. Measurement
    2. Metrics
2. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

February 2004

266 pages

ISBN:1581138296

DOI:10.1145/968280

General Chair:
Russ Tessier
University of Massachusetts -- Amherst
,
Program Chair:
Herman Schmit
Everychip, Inc.

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2004

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FPGA04

Sponsor:

FPGA04: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2004

February 22 - 24, 2004

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Upcoming Conference

FPGA '25

Sponsor:
sigda

The 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 27 - March 1, 2025

Monterey , CA , USA

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Cited By

Skordalakis EAttwood AGoodacre JLuján M(2024)AccProf: Increasing the Accuracy of Embedded Application Profiling Using FPGAsArchitecture of Computing Systems10.1007/978-3-031-66146-4_13(192-206)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-3-031-66146-4_13
Jaswal MRoy S(2022)DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path ProfilerIEEE Access10.1109/ACCESS.2022.321871010(116069-116086)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3218710
Dey MYilmaz BPrvulovic MZajic A(2021)PRIMER: Profiling Interrupts using Electromagnetic Side-Channel for Embedded DevicesIEEE Transactions on Computers10.1109/TC.2021.3109457(1-1)Online publication date: 2021
https://doi.org/10.1109/TC.2021.3109457
Azzouz BHadjira B(2021)Hardware/Software Codesign for Intelligent Motor Drive on an FPGA2020 2nd International Workshop on Human-Centric Smart Environments for Health and Well-being (IHSH)10.1109/IHSH51661.2021.9378712(227-232)Online publication date: 9-Feb-2021
https://doi.org/10.1109/IHSH51661.2021.9378712
Agirre JEtxeberria LBarbosa RBasagiannis SGiantamidis GBauer TFerrari EEsnaola MOrani VÖberg JPereira DProença JSchlick RSmrčka ATiberti WTonetta SBozzano MYazici ASangchoolie B(2021)The VALU3S ECSEL project: Verification and validation of automated systems safety and securityMicroprocessors and Microsystems10.1016/j.micpro.2021.104349(104349)Online publication date: Nov-2021
https://doi.org/10.1016/j.micpro.2021.104349
Jaswal MRoy S(2020)DynRP- Non-Intrusive Profiler for Dynamic Reconfigurability2020 24th International Symposium on VLSI Design and Test (VDAT)10.1109/VDAT50263.2020.9190415(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/VDAT50263.2020.9190415
Muttillo VValente GPomante LPosadas HMerino JVillar E(2020)Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow2020 23rd Euromicro Conference on Digital System Design (DSD)10.1109/DSD51259.2020.00029(117-125)Online publication date: Aug-2020
https://doi.org/10.1109/DSD51259.2020.00029
Suriano LMadronal DRodriguez AJuarez ESanz Cde la Torre E(2018)A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449389(1-8)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449389
Muttillo VValente GFederici FPomante LFaccio MTieri CFerri S(2016)A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling systemEURASIP Journal on Embedded Systems10.1186/s13639-016-0051-92016:1Online publication date: 15-Sep-2016
https://doi.org/10.1186/s13639-016-0051-9
Valente GMuttillo VPomante LFederici FFaccio MMoro AFerri STieri C(2016)A Flexible Profiling Sub-System for Reconfigurable Logic Architectures2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.86(373-376)Online publication date: Feb-2016
https://doi.org/10.1109/PDP.2016.86
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