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Tight bounds on the complexity of parallel sorting

Published: 01 December 1984 Publication History

Abstract

In this paper, we prove tight upper and lower bounds on the number or processors, information transfer, wire area and time needed to sort N numbers in a bounded-degree fixed-connection network. Our most important new results are:
1) the construction of an O(N))-node bounded-degree network capable of sorting N numbers in O(log N) word steps,
2) a proof that any network capable of sorting N(7 log N)-bit numbers in T bit-steps requires area A where AT2≥ Ω(N2log2N), and
3) the construction of a “small-constant-factor” bounded-degree network that sorts N θ(log N)-bit numbers in T = θ(log N) bit steps with A = θ(N2) area.

References

[1]
M. Ajtai, J. Komlos and E. Szemeredi, "An O (N log N) Sorting Network", Proc. 15th ACM Symp. on Theory of Computing, 1983, pp. 1-9.
[2]
D. Angluin and C. Thompson, unpublished manuscript, 1982.
[3]
K. Batcher, "Sorting Networks and their Applications", Proc. AFIPS Spring Joint Computer Conf., Vol. 32, 1968, pp 307-314.
[4]
G. Bilardi and F. Preparata, "An Architecture for Bitonic Sorting with Optimal VLSI Performance", IEEE Transactions on Computers, to appear.
[5]
G. Bilardi and F. Preparata, "A Minimum Area Architecture for O(log N) Time Sorting", Proc. 16th ACM Symp. on Theory of Computing, 1984, to appear.
[6]
G. Bilardi and F. Preparata, "The VLSI Optimality of the AKS Sorting Network," in preparation.
[7]
A. Borodin and J. Hoperoft, "Routing, Merging and Sorting on Parallel Models of Computation", Proc. 14th ACM Symp. on Theory of Computing, 1982, pp. 338-344.
[8]
A. El Gamal, personal communication, 1983.
[9]
D. Knuth, The Art of Computer Programming: Sorting and Searching, Addison-Wesley.
[10]
F. T. Leighton, "New Lower Bound Techniques for VLSI," Proc. 22nd Conf. on Foundations of Computer Science, 1981, pp. 1-12.
[11]
F. T. Leighton, Complexity Issues in VLSI: Optimal Layouts for the Shuffle-Exchange Graph and Other Networks, MIT Press, 1983.
[12]
F. T. Leighton, "Parallel Computation Using Meshes of Trees", Proc. 1983 Workshop on Graphtheoretic Concepts in Computer Science, Osnabruck West Germany.
[13]
F. T. Leighton, "Simple o(log2N)-Depth Sorting Circuits", in preparation.
[14]
R. Lipton and R. Sedgewick, "Lower Bounds for VLSI", Proc. 19th ACM Symp. on Theory of Computing, 1981, pp. 300-307.
[15]
D. S. Parker, "Notes on Shuffle/Exchange-Type Switching Networks", IEEE Transactions on Computers, Vol. C-29, No. 3, 1980, pp. 213-222.
[16]
J. Reif and L. Valiant, "A Logarithmic Time Sort for Linear Size Networks" Proc. 15th ACM Symp. on Theory of Computing, 1983, pp. 10-16.
[17]
H. Stone, "Parallel Processing with the Perfect Shuffle", IEEE Transactions on Computers, Vol. C-20, No. 2, 1971.
[18]
C. Thompson, "Area-Time Complexity for VLSI", Proc. 11th ACM Symp. on Theory of Computing, 1979, pp. 81-88.
[19]
C. Thompson, "The VLSI Complexity of Sorting", IEEE Transactions on Computers, Vol. C-32, No. 12, 1983.
[20]
J. Ullman, Computational Aspects of VLSI, Computer Science Press, 1983.
[21]
L. Valiant and G. Brebner, "Universal Schemes for Parallel Communication", Proc. 19th ACM Symp. on Theory of Computing, 1981, pp. 263-277.

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cover image ACM Conferences
STOC '84: Proceedings of the sixteenth annual ACM symposium on Theory of computing
December 1984
547 pages
ISBN:0897911334
DOI:10.1145/800057
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 December 1984

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Cited By

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  • (2023)Anonymous Permutation RoutingTheory of Cryptography10.1007/978-3-031-48621-0_2(33-61)Online publication date: 27-Nov-2023
  • (2022)Differentially Oblivious Data Analysis With Intel SGX: Design, Optimization, and EvaluationIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2021.310631719:6(3741-3758)Online publication date: 1-Nov-2022
  • (2022)Hypersort: High-performance Parallel Sorting on HBM-enabled FPGA2022 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT56656.2022.9974209(1-11)Online publication date: 5-Dec-2022
  • (2020)Oblivious coopetitive analytics using hardware enclavesProceedings of the Fifteenth European Conference on Computer Systems10.1145/3342195.3387552(1-17)Online publication date: 15-Apr-2020
  • (2017)Computer Generation of High Throughput and Memory Efficient Sorting Designs on FPGAIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.270512828:11(3100-3113)Online publication date: 1-Nov-2017
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  • (2015)Energy and Memory Efficient Mapping of Bitonic Sorting on FPGAProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689068(240-249)Online publication date: 22-Feb-2015
  • (2015)A hybrid design for high performance large-scale sorting on FPGA2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393322(1-6)Online publication date: Dec-2015
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  • (2014)Zig-zag sortProceedings of the forty-sixth annual ACM symposium on Theory of computing10.1145/2591796.2591830(684-693)Online publication date: 31-May-2014
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