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Article

Adapting instruction level parallelism for optimizing leakage in VLIW architectures

Authors:

N. Vijaykrishnan,

M. J. IrwinAuthors Info & Claims

LCTES '03: Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems

Pages 275 - 283

https://doi.org/10.1145/780732.780770

Published: 11 June 2003 Publication History

Abstract

Due to ever increasing number of transistors and decreasing threshold voltages, leakage energy consumption is expected to play a decisive role in the next generation circuits. We believe that software support is a must to exploit available leakage control mechanisms. In this paper, we present and evaluate a compiler-oriented leakage optimization strategy based on tuning IPC (instructions ---issued--- per cycle) at a loop-level granularity according to the needs of application. Once a suitable IPC is selected for each loop, our strategy turns off unused or not frequently used integer ALUs to save leakage energy. Our preliminary results indicate that our technique can reduce up to 38% of the functional unit leakage energy across a range of VLIW configurations. Our results also show that our loop based IPC detection strategy gives better energy-delay product than finer-granularity (basic block level) and coarser-granularity (whole application level) IPC detection schemes.

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Cited By

Ma Y(2020)Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy OptimizationIEEE Access10.1109/ACCESS.2019.29615688(1733-1754)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2019.2961568
Tong YZhang WMa YLiu YLiang YZhang TLuo H(2017)Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP ProcessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263641925:4(1329-1341)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2636419
Kondo MKobyashi HSakamoto RWada MTsukamoto JNamiki MWang WAmano HMatsunaga KKudo MUsami KKomoda TNakamura HFettweis GNebel W(2014)Design and evaluation of fine-grained power-gating for embedded microprocessorsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616785(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616785
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Index Terms

Adapting instruction level parallelism for optimizing leakage in VLIW architectures
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Information & Contributors

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Published In

cover image ACM Conferences

LCTES '03: Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems

June 2003

304 pages

ISBN:1581136471

DOI:10.1145/780732

General Chair:
Frank Mueller
North Carolina State University
,
Publications Chair:
Uli Kremer
Rutgers University

ACM SIGPLAN Notices Volume 38, Issue 7
Special Issue: Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool support for embedded systems (San Diego, CA).
July 2003
293 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/780731
Issue’s Table of Contents

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 June 2003

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LCTES03

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LCTES03: ACM SIGPLAN Symposium on Languages, Compilers, and Tools for Embedded Systems

June 11 - 13, 2003

California, San Diego, USA

Acceptance Rates

LCTES '03 Paper Acceptance Rate 29 of 128 submissions, 23%;

Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

Ma Y(2020)Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy OptimizationIEEE Access10.1109/ACCESS.2019.29615688(1733-1754)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2019.2961568
Tong YZhang WMa YLiu YLiang YZhang TLuo H(2017)Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP ProcessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.263641925:4(1329-1341)Online publication date: 1-Apr-2017
https://dl.acm.org/doi/10.1109/TVLSI.2016.2636419
Kondo MKobyashi HSakamoto RWada MTsukamoto JNamiki MWang WAmano HMatsunaga KKudo MUsami KKomoda TNakamura HFettweis GNebel W(2014)Design and evaluation of fine-grained power-gating for embedded microprocessorsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616785(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616785
Liang ZZhang WMa Y(2014)Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register FilesACM Transactions on Architecture and Code Optimization10.1145/263221811:2(1-26)Online publication date: 15-Jul-2014
https://dl.acm.org/doi/10.1145/2632218
Yang X(2014)Path-Dividing Based Scheduling Algorithm for Reducing Energy Consumption of Clustered VLIW ArchitecturesIEEE Transactions on Computers10.1109/TC.2013.13863:10(2526-2539)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1109/TC.2013.138
Ma YChao WLiu T(2014)Enabling energy-proportional computing on instruction-level parallel processorsThe Journal of Supercomputing10.1007/s11227-014-1301-z71:2(391-447)Online publication date: 5-Oct-2014
https://doi.org/10.1007/s11227-014-1301-z
Bahuleyan JNagpal RSrikant Y(2010)Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)10.1109/IPDPSW.2010.5470906(1-8)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPSW.2010.5470906
Carrion Schafer BKim T(2009)Autonomous temperature control technique in VLSI circuits through logic replicationIET Computers & Digital Techniques10.1049/iet-cdt:200701593:1(62)Online publication date: 2009
https://doi.org/10.1049/iet-cdt:20070159
Youssef AAnis MElmasry M(2008)A comparative study between static and dynamic sleep signal generation techniques for leakage tolerant designsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200073016:9(1114-1126)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000730
Wang MShao ZLiu HXue C(2008)Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP ProcessorsDistributed Embedded Systems: Design, Middleware and Resources10.1007/978-0-387-09661-2_11(111-120)Online publication date: 2008
https://doi.org/10.1007/978-0-387-09661-2_11
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