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Verification of timing constraints on large digital systems

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T. McWilliamsAuthors Info & Claims

25 years of DAC: Papers on Twenty-five years of electronic design automation

Pages 388 - 396

https://doi.org/10.1145/62882.62928

Published: 01 June 1988 Publication History

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References

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Cited By

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Ulrich EHebert D(1982)Speed and Accuracy in Digital Network Simulation Based on Structural Modeling19th Design Automation Conference10.1109/DAC.1982.1585557(587-593)Online publication date: 1982
https://doi.org/10.1109/DAC.1982.1585557
Bass SGrundmann J(1981)Expected value analysis of combinational logic networksIEEE Transactions on Circuits and Systems10.1109/TCS.1981.108499928:5(367-382)Online publication date: May-1981
https://doi.org/10.1109/TCS.1981.1084999

Index Terms

Verification of timing constraints on large digital systems
1. Hardware
  1. Hardware validation
    1. Functional verification

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DAC '80: Proceedings of the 17th Design Automation Conference

A new approach to the verification of the timing constraints on large digital systems has been developed. The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous ...
Verification of timing constraints on large digital systems
Feasibility of semiring-based timing constraints

Real-time and embedded applications often involve different types of timing constraints, such as precedence constraints and real-time constraints. As real-time and embedded applications further advance, new timing constraint types are emerging as well. ...

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25 years of DAC: Papers on Twenty-five years of electronic design automation

June 1988

630 pages

ISBN:0897912675

DOI:10.1145/62882

Editor:
A. R. Newton

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1988

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Ulrich EHebert D(1982)Speed and Accuracy in Digital Network Simulation Based on Structural Modeling19th Design Automation Conference10.1109/DAC.1982.1585557(587-593)Online publication date: 1982
https://doi.org/10.1109/DAC.1982.1585557
Bass SGrundmann J(1981)Expected value analysis of combinational logic networksIEEE Transactions on Circuits and Systems10.1109/TCS.1981.108499928:5(367-382)Online publication date: May-1981
https://doi.org/10.1109/TCS.1981.1084999

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Verification of timing constraints on large digital systems

Verification of timing constraints on large digital systems

Feasibility of semiring-based timing constraints