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Article

Scheduler-based DRAM energy management

Authors:

A. Sivasubramaniam,

N. Vijaykrishnan,

M. J. IrwinAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 697 - 702

https://doi.org/10.1145/513918.514095

Published: 10 June 2002 Publication History

Abstract

Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operating modes. While hardware-based techniques require extra logic to keep track of memory references and make decisions about future mode transitions, compiler-directed schemes can only work on a single application at a time and demand sophisticated program analysis support. In this work, we present an operating system (OS) based solution where the OS scheduler directs the power mode transitions by keeping track of module accesses for each process in the system. This global view combined with the flexibility of a software approach brings large energy savings at no extra hardware cost. Our implementation using a full-fledged OS shows that the proposed technique is also very robust when different system and workload parameters are modified, and provides the first set of experimental results for memory energy optimization with a multiprogrammed workload on a real platform. The proposed technique is applicable to both embedded systems and high-end computing platforms.

References

[1]

L. Benini, A. Bogliolo, and G. D. Micheli. A survey of design techniques for system-level dynamic power management. IEEE Transactions on VLSI Systems, 8(3), June 2000.]]

Digital Library

[2]

F. Catthoor, S. Wuytack, E. D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom Memory Management Methodology -- Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic Publishers, June 1998.]]

Digital Library

[3]

V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. Hardware and software techniques for controlling DRAM power modes. IEEE Transactions on Computers, November 2001 (Vol.50,No.11).]]

Digital Library

[4]

K. Govil, E. Chan, and H. Wasserman. Comparing algorithms for dynamic speed-setting of a low-power CPU. In Proc. the ACM International Conference on Mobile Computing and Networking, pages 13--25, 1995.]]

Digital Library

[5]

I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava. Power optimization of variable voltage core-based systems. In Proc. Design Automation Conf., 1998.]]

Digital Library

[6]

Intel announcement. http://developer.intel.com/design/mobile/intelpower/int_mpg.htm.]]

[7]

Intel announcement. http://www.intel.com/pressroom/archive/releases/20011126tech.htm]]

[8]

M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye. Influence of compiler optimizations on system power. In Proc. the 37th Design Automation Conference, Los Angeles, California USA, June 5-9, 2000.]]

Digital Library

[9]

A. R. Lebeck, X. Fan, H. Zeng, and C. S. Ellis. Power aware page allocation. In Proc. ASPLOS'00, November 2000.]]

Digital Library

[10]

C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communication systems. In Proc. The International Symposium on Microarchitecture, 1997.]]

Digital Library

[11]

J. R. Lorch and A. J. Smith. Scheduling techniques for reducing processor energy use in MacOS. Wireless Networks, 3(5):311--324, 1997.]]

Digital Library

[12]

Y.-H. Lu, L. Benini, and G. De Micheli. Operating system-directed power reduction. In Proc. ISLPED'00, Rapallo, Italy, 2000.]]

Digital Library

[13]

Rambus Inc. http://www.rambus.com/.]]

[14]

128/144-MBit Direct RDRAM Data Sheet, Rambus Inc., 1999.]]

[15]

Y. Shin and K. Choi. Power-conscious fixed priority scheduling for hard real-time systems. In Proc. Design Automation Conference, pages 134--139, 1999.]]

Digital Library

[16]

N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Y. Kim, and W. Ye. Energy driven integrated hardware-software optimizations using SimplePower. In Proc. the International Symposium on Computer Architecture, June 2000.]]

Digital Library

[17]

M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced CPU energy. In Proc. Symposium on Operating Systems Design and Implementation, pages 13--23, 1994.]]

Digital Library

[18]

W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. The design and use of SimplePower: a cycle-accurate energy estimation tool. In Proc. the 37th Design Automation Conference, Los Angeles, California USA, June 5-9, 2000.]]

Digital Library

[19]

M. Beck.phLinux Kernel Internals (2nd Edition). Addison-Wesley, 1999.]]

Digital Library

Cited By

Yahya JVolos HBartolini DAntoniou GKim JWang ZKalaitzidis KRollet TChen ZGeng YMutlu OSazeides Y(2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00063
Salami BNoori HNaghibzadeh M(2022)Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contentionThe Journal of Supercomputing10.1007/s11227-021-04159-878:6(7729-7748)Online publication date: 3-Jan-2022
https://doi.org/10.1007/s11227-021-04159-8
Karyakin ASalem K(2019)DimmStoreProceedings of the VLDB Endowment10.14778/3342263.3342262912:11(1499-1512)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.14778/3342263.33422629
Show More Cited By

Index Terms

Scheduler-based DRAM energy management
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
2. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Scheduling

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Published In

cover image ACM Conferences

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2002

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DAC02

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SIGDA

DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Yahya JVolos HBartolini DAntoniou GKim JWang ZKalaitzidis KRollet TChen ZGeng YMutlu OSazeides Y(2022)AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO56248.2022.00063(835-850)Online publication date: Oct-2022
https://doi.org/10.1109/MICRO56248.2022.00063
Salami BNoori HNaghibzadeh M(2022)Online energy-efficient fair scheduling for heterogeneous multi-cores considering shared resource contentionThe Journal of Supercomputing10.1007/s11227-021-04159-878:6(7729-7748)Online publication date: 3-Jan-2022
https://doi.org/10.1007/s11227-021-04159-8
Karyakin ASalem K(2019)DimmStoreProceedings of the VLDB Endowment10.14778/3342263.3342262912:11(1499-1512)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.14778/3342263.33422629
Olson MTeague JRao DJANTZ MDoshi KKulkarni P(2018)Cross-Layer Memory Management to Improve DRAM Energy EfficiencyACM Transactions on Architecture and Code Optimization10.1145/319688615:2(1-27)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1145/3196886
Chandrasekharan SGniady CEl-Araby EEl-Ghazawi TPanda D(2018)QAMEMProceedings of the 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing10.1109/CCGRID.2018.00068(412-421)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1109/CCGRID.2018.00068
Karyakin ASalem K(2017)An analysis of memory power consumption in database systemsProceedings of the 13th International Workshop on Data Management on New Hardware10.1145/3076113.3076117(1-9)Online publication date: 14-May-2017
https://dl.acm.org/doi/10.1145/3076113.3076117
Lu YWu DHe BTang XXu JGuo M(2016)Rank-Aware Dynamic Migrations and Adaptive Demotions for DRAM Power ManagementIEEE Transactions on Computers10.1109/TC.2015.240984765:1(187-202)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TC.2015.2409847
Li ZChen MMukker AZadok E(2015)On the Trade-Offs among Performance, Energy, and Endurance in a Versatile Hybrid DriveACM Transactions on Storage10.1145/270031211:3(1-27)Online publication date: 24-Jul-2015
https://dl.acm.org/doi/10.1145/2700312
Yanchao Lu Bingsheng He Xueyan Tang Minyi Guo (2015)Synergy of Dynamic Frequency Scaling and Demotion on DRAM Power Management: Models and OptimizationsIEEE Transactions on Computers10.1109/TC.2014.236053464:8(2367-2381)Online publication date: 1-Aug-2015
https://dl.acm.org/doi/10.1109/TC.2014.2360534
Park SMaeng MPark KPark K(2014)Adaptive wear-leveling algorithm for PRAM main memory with a DRAM bufferACM Transactions on Embedded Computing Systems10.1145/255842713:4(1-25)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2558427
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