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short-paper

CIM-SIM: Computation In Memory SIMuIator

Authors:

Kanishkan Vadivel,

Henk Corporaal,

Muath Abu Lebdeh,

Said HamdiouiAuthors Info & Claims

SCOPES '19: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems

Pages 1 - 4

https://doi.org/10.1145/3323439.3323989

Published: 27 May 2019 Publication History

Abstract

Computation-in-memory reverses the trend in von-Neumann processors by bringing the computation closer to the data, to even within the memory array, as opposed to introducing new memory hierarchies to keep (frequently used) data closer to a central processing unit (CPU). In recent years, new non-volatile memory (NVM) technologies, e.g., memristor, PCM, etc., have proven that they can function as memories and perform computations on the stored data as well. In particular, when they are combined with a modest set of (digital) peripheral modules, a wider range of operations can be supported, e.g., vector matrix multiply and Boolean logic. In this paper, we are introducing the CIM-SIM, an open source simulator written in SystemC, which is capable of simulating the functional behaviour of such architectures. The architecture includes the definition of a set of technology-agnostic nano-instructions.

References

[1]

Muath Abu Lebdeh, Uljana Reinsalu, Hoang Anh Du Nguyen, Stephan Wong, and Said Hamdioui. 2019. Memristive Device Based Circuits for Computation-in-Memory Architectures. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Accepted (Paper ID: 5782769).

[2]

Fabien Alibart, Ligang Gao, Brian D Hoskins, and Dmitri B Strukov. 2012. High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm. Nanotechnology 23, 7 (2012), 075201.

[3]

Md Zahangir Alom, Tarek M Taha, Christopher Yakopcic, Stefan Westberg, Mahmudul Hasan, Brian C Van Esesn, Abdul A S Awwal, and Vijayan K Asari. 2018. The history began from alexnet: A comprehensive survey on deep learning approaches. arXiv preprint arXiv:1803.01164 (2018).

[4]

Irem Boybat, Manuel Le Gallo, SR Nandakumar, Timoleon Moraitis, Thomas Parnell, Tomas Tuma, Bipin Rajendran, Yusuf Leblebici, Abu Sebastian, and Evangelos Eleftheriou. 2018. Neuromorphic computing with multi-memristive synapses. Nature communications 9, 1 (2018), 2514.

[5]

Yunji Chen, Tao Luo, Shaoli Liu, Shijin Zhang, Liqiang He, Jia Wang, Ling Li, Tianshi Chen, Zhiwei Xu, Ninghui Sun, and Olivier Temam. 2014. DaDianNao: A Machine-Learning Supercomputer. In Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-47). IEEE Computer Society, Washington, DC, USA, 609--622.

Digital Library

[6]

Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory. In Proceedings of the 43rd International Symposium on Computer Architecture (ISCA '16). IEEE Press, Piscataway, NJ, USA, 27--39.

Digital Library

[7]

Jerry Chou, Mark Howison, Brian Austin, Kesheng Wu, Ji Qiang, E. Wes Bethel, Arie Shoshani, Oliver Rübel, Prabhat, and Rob D. Ryne. 2011. Parallel Index and Query for Large Scale Data Analysis. In Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC '11). ACM, New York, NY, USA, Article 30, 11 pages.

Digital Library

[8]

Miao Hu, John Paul Strachan, Zhiyong Li, R Stanley, et al. 2016. Dot-product engine as computing memory to accelerate machine learning algorithms. In 2016 17th International Symposium on Quality Electronic Design (ISQED). IEEE, 374--379.

[9]

Manuel Le Gallo, Abu Sebastian, Roland Mathis, Matteo Manica, Heiner Giefers, Tomas Tuma, Costas Bekas, Alessandro Curioni, and Evangelos Eleftheriou. 2018. Mixed-precision in-memory computing. Nature Electronics 1, 4 (2018), 246.

[10]

Can Li, Miao Hu, Yunning Li, Hao Jiang, Ning Ge, Eric Montgomery, Jiaming Zhang, Wenhao Song, Noraica Dávila, Catherine E Graves, et al. 2018. Analogue signal and image processing with large memristor crossbars. Nature Electronics 1, 1 (2018), 52.

[11]

Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, and Yuan Xie. 2016. Pinatubo: A Processing-in-memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories. In Proceedings of the 53rd Annual Design Automation Conference (DAC '16). ACM, New York, NY, USA, Article 173, 6 pages.

Digital Library

[12]

Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, and Tianshi Chen. 2016. Cambricon: An Instruction Set Architecture for Neural Networks. In Proceedings of the 43rd International Symposium on Computer Architecture (ISCA '16). IEEE Press, Piscataway, NJ, USA, 393--405.

Digital Library

[13]

Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, and Vivek Srikumar. 2016. ISAAC: A Convolutional Neural Network Accelerator with In-situ Analog Arithmetic in Crossbars. In Proceedings of the 43rd International Symposium on Computer Architecture (ISCA '16). IEEE Press, Piscataway, NJ, USA, 14--26.

Digital Library

[14]

John M Shalf and Robert Leland. 2015. Computing beyond Moore's Law. Computer 48, 12 (2015), 14--23.

Digital Library

[15]

R Stanley Williams. 2017. What's Next? {The end of Moore's law}. Computing in Science Engineering 19, 2 (2017), 7--13.

Digital Library

[16]

H-S Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T Chen, and Ming-Jinn Tsai. 2012. Metal--oxide RRAM. Proc. IEEE 100, 6 (2012), 1951--1970.

[17]

Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, and Huazhong Yang. 2018. MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 5, 1009--1022.

[18]

Lei Xie, Hoang Anh Du Nguyen, Jintao Yu, Ali Kaichouhi, Mottaqiallah Taouil, Mohammad AlFailakawi, and Said Hamdioui. 2017. Scouting logic: A novel memristor-based logic design for resistive computing. In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 176--181.

Cited By

Park JKim BSung H(2024)NavCim: Comprehensive Design Space Exploration for Analog Computing-in-Memory ArchitecturesProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676946(168-182)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676946
Roohi ATabrizchi SMorsali MPan DAngizi S(2024)PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330557443:1(141-150)Online publication date: Jan-2024
https://doi.org/10.1109/TCAD.2023.3305574
Yu KKim SChoi J(2024)Trends and Challenges in Computing-in-Memory for Neural Network Model: A Review From Device Design to Application-Side OptimizationIEEE Access10.1109/ACCESS.2024.351149212(186679-186702)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3511492
Show More Cited By

Index Terms

CIM-SIM: Computation In Memory SIMuIator
1. Computing methodologies
  1. Modeling and simulation
    1. Simulation support systems
      1. Simulation tools
2. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging architectures
    2. Memory and dense storage
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific instruction set processors

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SCOPES '19: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems

May 2019

100 pages

ISBN:9781450367622

DOI:10.1145/3323439

Editor:
Sander Stuijk
Eindhoven University of Technology, The Netherlands

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAA: European Design Automation Association

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SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 May 2019

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Short-paper
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Refereed limited

Funding Sources

Horizon 2020

Conference

SCOPES '19

Sponsor:

EDAA

SCOPES '19: 22nd International Workshop on Software and Compilers for Embedded Systems

May 27 - 28, 2019

Sankt Goar, Germany

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Overall Acceptance Rate 38 of 79 submissions, 48%

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Cited By

Park JKim BSung H(2024)NavCim: Comprehensive Design Space Exploration for Analog Computing-in-Memory ArchitecturesProceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques10.1145/3656019.3676946(168-182)Online publication date: 14-Oct-2024
https://dl.acm.org/doi/10.1145/3656019.3676946
Roohi ATabrizchi SMorsali MPan DAngizi S(2024)PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330557443:1(141-150)Online publication date: Jan-2024
https://doi.org/10.1109/TCAD.2023.3305574
Yu KKim SChoi J(2024)Trends and Challenges in Computing-in-Memory for Neural Network Model: A Review From Device Design to Application-Side OptimizationIEEE Access10.1109/ACCESS.2024.351149212(186679-186702)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3511492
Aguirre FSebastian ALe Gallo MSong WWang TYang JLu WChang MIelmini DYang YMehonic AKenyon AVillena MRoldán JWu YHsu HRaghavan NSuñé JMiranda EEltawil ASetti GSmagulova KSalama KKrestinskaya OYan XAng KJain SLi SAlharbi OPazos SLanza M(2024)Hardware implementation of memristor-based artificial neural networksNature Communications10.1038/s41467-024-45670-915:1Online publication date: 4-Mar-2024
https://doi.org/10.1038/s41467-024-45670-9
Galicia MOsman IOwusu-Afriyie CLeupers RPayvand MParsa MSchuman C(2023)"S3cure": Scramble, Shuffle and Shambles - Secure Deployment of Weight Matrices in Memristor Crossbar ArraysProceedings of the 2023 International Conference on Neuromorphic Systems10.1145/3589737.3605964(1-8)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1145/3589737.3605964
Zhu ZSun HXie TZhu YDai GXia LNiu DChen XHu XCao YXie YYang HWang Y(2023)MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325169642:11(4112-4125)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3251696
Park JShin YSung H(2023)Multi-Objective Architecture Search and Optimization for Heterogeneous Neuromorphic Architecture2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323779(1-8)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323779
Mishra VKumar AAkashe S(2023)New Non-Volatile Memory Technologies and Neuromorphic Computing2023 IEEE World Conference on Applied Intelligence and Computing (AIC)10.1109/AIC57670.2023.10263872(857-862)Online publication date: 29-Jul-2023
https://doi.org/10.1109/AIC57670.2023.10263872
Kao HHuang SCheng W(2022)Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware EvaluationElectronics10.3390/electronics1113210711:13(2107)Online publication date: 5-Jul-2022
https://doi.org/10.3390/electronics11132107
Staudigl FMerchant FLeupers R(2022)A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and SecurityIEEE Design & Test10.1109/MDAT.2021.310201339:2(90-99)Online publication date: Apr-2022
https://doi.org/10.1109/MDAT.2021.3102013
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