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LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field

Published: 13 May 2019 Publication History

Abstract

Unified (hybrid field-size) systolic multiplier over GF(2m) (binary extension field) has attracted significant attentions from research communities recently as it can be used in reconfigurable cryptographic processors. In this paper, we present a novel Low-complexity unified Systolic Multiplier (LSM) design strategy to address the above mentioned challenge. First, a novel multiplication algorithm for unified implementation is proposed first with detailed mathematical derivation. Then, an efficient systolic structure is then presented based on the proposed algorithm (with the help of several mapping techniques). Finally, a thorough complexity analysis is given to verify the superior performance of the proposed design (the proposed structure involves better complexities than the newly reported design).

References

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Haining et al. Fan. 2007. A new approach to subquadratic space complexity parallel multipliers for extended binary fields. IEEE Trans. Computers 56, 2 (2007), 224--233.
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FIPS. 2000. 186-2. Digital Signature Standard. US Department of Commerce/National Institute of Standards and Technology.
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Kwiat, G, and Gauthier, J. 2017. Reconfigurable Free-Space Quantum Cryptography System. US Patent App. 15/434,313.
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Qiliang et al. Shao. 2018. Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m). IEEE TCASI 65, 8 (2018), 2455--2465.
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Nangate standard cell library. {n. d.}. {Online}. Available: http://www.si2.org/openeda.si2.org/projects/nangatelib.
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Jiafeng et al. Xie. 2013. Low latency systolic Montgomery multiplier for finite field GF(2m) based on pentanomials. IEEE Trans. VLSI Systems 21, 2 (2013), 385--389.
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Yiqun et al. Zhang. 2017. Recryptor: A reconfigurable in-memory cryptographic Cortex-M0 processor for IoT. In VLSI Circuits, 2017 Symposium on. IEEE, C264--C265

Cited By

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  • (2020)Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2) based on Bivariate Polynomial Basis RepresentationProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045615(253-258)Online publication date: 17-Jan-2020

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Published In

cover image ACM Conferences
GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI
May 2019
562 pages
ISBN:9781450362528
DOI:10.1145/3299874
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 May 2019

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Author Tags

  1. binary extension field
  2. fast algorithm
  3. finite field multiplier
  4. systolic structure
  5. unified implementation

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  • Research-article

Funding Sources

  • Villanova Internal Fund

Conference

GLSVLSI '19
Sponsor:
GLSVLSI '19: Great Lakes Symposium on VLSI 2019
May 9 - 11, 2019
VA, Tysons Corner, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

View all
  • (2020)Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2) based on Bivariate Polynomial Basis RepresentationProceedings of the 25th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC47756.2020.9045615(253-258)Online publication date: 17-Jan-2020

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